STM32F413XG datasheet(38/207 Pages) STMICROELECTRONICS

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Functional overview

STM32F413xG/H

38/207

DocID029162 Rev 2

3.25

Serial peripheral interface (SPI)

The devices feature five SPIs in slave and master modes in full-duplex and simplex

communication modes. SPI1, SPI4 and SPI5 can communicate at up to 50 Mbit/s, SPI2 and

SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode

frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC

generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the

DMA controller.

The SPI interfaces can be configured to operate in TI mode for communications in master

mode and slave mode.

3.26

Inter-integrated sound (I2S)

Five standard I2S interfaces (multiplexed with SPI1 to SPI5) are available. They can be

operated in master or slave mode, in simplex communication mode, and full duplex mode

for I2S2 and I2S3. All I2S interfaces can be configured to operate with a 16-/32-bit resolution

as an input or output channel. I2Sx audio sampling frequencies from 8 kHz up to 192 kHz

are supported. When either or both of the I2S interfaces is/are configured in master mode,

the master clock can be output to the external DAC/CODEC at 256 times the sampling

frequency.

All I2Sx interfaces can be served by the DMA controller.

3.27

Serial Audio interface (SAI1)

The serial audio interface (SAI1) is based on two independent audio sub-blocks which can

operate as transmitter or receiver with their FIFO. Many audio protocols are supported by

each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF

output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both sub-blocks

can be configured in master or in slave mode.

In master mode, the master clock can be output to the external DAC/CODEC at 256 times of

the sampling frequency.

The two sub-blocks can be configured in synchronous mode when full-duplex mode is

required.

SAI1 can be served by the DMA controller.

3.28

Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows

to achieve error-free I2S sampling clock accuracy without compromising on the CPU

performance, while using USB peripherals.

Different sources can be selected for the I2S master clock of the APB1 and the I2S master

clock of the APB2. This gives the flexibility to work with two different audio sampling

frequencies. The different possible sources are the main PLL, the PLLI2S, HSE or HSI

clocks or an external clock provided through a pin (external PLL or CODEC output)

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