MIC4607 datasheet(18/42 Pages) MICROCHIP

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MIC4607

DS20005610A-page 18

 2016 Microchip Technology Inc.

4.3

PWM Input Mode (MIC4607-2)

A low going xPWM signal applied to the MIC4607-2

causes xHO to go low, typically 35ns (tHOOFF) after the

xPWM input goes low, at which point the switch node,

xHS, falls (1 – 2).

When xHS reaches 2.2V (VSWTH), the external

high-side MOSFET is deemed off and xLO goes high,

typically within 35 ns (tLOON) (3-4). xHS falling below

2.2V sets a latch that can only be reset by xPWM going

high. This design prevents ringing on xHS from causing

an indeterminate xLO state. Should xHS never trip the

aforementioned internal comparator reference (2.2V),

a falling xPWM edge delayed by 250 ns will set “HS

latch” allowing xLO to go high.

A 35 ns delay gated by xPWM going low can determine

the time to xLO going high for fast falling HS designs.

xPWM going high forces xLO low in typically 35ns

(tLOOFF) (5 – 6).

When xLO reaches 1.9V (VLOOFF), the low-side MOS-

FET is deemed off and xHO is allowed to go high. The

delay between these two points is typically 35 ns

(tHOON) (7 – 8).

xHO and xLO output rise and fall times (tR/tF) are typi-

cally 20 ns driving 1000 pF capacitive loads.

FIGURE 4-3:

PWM Mode (MIC4607-2).

tLOOFF

(VLOOFF)

tHOON

xHS

xHO

xLO

xPWM

tLOON

tHOOFF

(VSWTH)

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