6

DS580F6

CS8406

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS

Notes:

5. The active edge of ISCLK is programmable in Software Mode.

6. The polarity of ILRCK is programmable in Software Mode.

7. Prevents the previous ISCLK edge from being interpreted as the first one after ILRCK has changed.

8. This setup time ensures that this ISCLK edge is interpreted as the first one after ILRCK has changed.

Parameter

Symbol

Min

Typ

Max

Units

SDIN Setup Time Before ISCLK Active Edge

(Note 5)

10

-

-

ns

SDIN Hold Time After ISCLK Active Edge

(Note 5)

8-

-

ns

Master Mode

OMCK to ISCLK active edge delay

(Note 5)

0-

17

ns

OMCK to ILRCK delay

(Note 6)

0-

16

ns

ISCLK and ILRCK Duty Cycle

-

50

-

%

Slave Mode

ISCLK Period

36

-

-

ns

ISCLK Input Low Width

14.4

-

-

ns

ISCLK Input High Width

14.4

-

-

ns

ISCLK Active Edge to ILRCK Edge

(Note 7)

10

-

-

ns

ILRCK Edge Setup Before ISCLK Active Edge

(Note 8)

10

-

-

ns

ISCLK

ILRCK

(output)

(output)

OMCK

(input)

t smd

t lmd

sckh

sckl

sckw

t

t

t

(input)

(input)

SDIN

dh

t

ds

t

lrcks

t

lrckd

t

ISCLK

ILRCK

Figure 1. Audio Port Master Mode Timing

Figure 2. Audio Port Slave Mode and Data Input Timing