CS8406-CSZ datasheet(21/39 Pages) CIRRUS

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DS580F6

CS8406

Default = ‘00’

00 - OMCK frequency is 256*Fs

01 - OMCK frequency is 384*Fs

10 - OMCK frequency is 512*Fs

11 - OMCK frequency is 128*Fs

8.6

Serial Audio Input Port Data Format (05h)

SIMS - Master/Slave Mode Selector

Default = ‘0’

0 - Serial audio input port is in Slave Mode

1 - Serial audio input port is in Master Mode

SISF - ISCLK frequency (for Master Mode)

Default = ‘0’

0 - 64*Fs

1 - 128*Fs

SIRES1:0 - Resolution of the input data, for right-justified formats

Default = ‘00’

00 - 24-bit resolution

01 - 20-bit resolution

10 - 16-bit resolution

11 - Reserved

SIJUST - Justification of SDIN data relative to ILRCK

Default = ‘0’

0 - Left-justified

1 - Right-justified

SIDEL - Delay of SDIN data relative to ILRCK, for left-justified data formats

Default = ‘0’

0 - MSB of SDIN data occurs in the first ISCLK period after the ILRCK edge (Left-Justified Mode)

1 - MSB of SDIN data occurs in the second ISCLK period after the ILRCK edge (I²S Mode)

SISPOL - ISCLK clock polarity

Default = ‘0’

0 - SDIN sampled on rising edges of ISCLK

1 - SDIN sampled on falling edges of ISCLK

SILRPOL - ILRCK clock polarity

Default = ‘0’

0 - SDIN data is for the left channel when ILRCK is high

1 - SDIN data is for the right channel when ILRCK is high

SIMS

SISF

SIRES1

SIRES0

SIJUST

SIDEL

SISPOL

SILRPOL

CS8406-CSZ 数据表(PDF) 21 Page - Cirrus Logic

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CS8406-CSZ 数据表(PDF) 21 Page - Cirrus Logic

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