30

DS580F6

CS8406

SFMT0

SFMT1

4

5

Serial Audio Data Format Select (Input) - Selects the serial audio input port format. See Table 3 on

page 28.

APMS

10 Serial Audio Data Port Master/Slave Select (

Input

) - APMS should be connected to VL to set serial

audio input port as a master or connected to GND to set the port as a slave.

HWCK0

HWCK1

20

27

OMCK Clock Ratio Select (Input) - Selects the ratio of OMCK to the input sample rate (Fs). A pull-up to

VL or pull-down to GND is required to set the appropriate mode. See Table 4 on page 28.

TCBLD

11 Transmit Channel Status Block Direction (

Input

) - Connect TCBLD to VL to set TCBL as an output.

Connect TCBLD to GND to set TCBL as an input.

TCBL

15

Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during

the first sub-frame of a transmitted channel status block, and low at all other times. When operated as

input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be

the start of a channel status block.

CEN

16

C Bit Enable (Input) - Determines how the channel status data bits are input. When CEN is low, Hard-

ware Mode A is selected, where the COPY/C, ORIG, EMPH and AUDIO pins are used to enter selected

channel status data. When CEN is high, Hardware Mode B is selected, where the COPY/C pin is used

to enter serial channel status data.

V

17 Validity Bit (

Input

) - In Hardware Modes A and B, the V pin input determines the state of the validity bit

in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK.

U

18 User Data Bit (

Input

) - In Hardware Modes A and B, the U pin input determines the state of the user

data bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK.

COPY/C

1

COPY Channel Status Bit/C Bit (Input) - In Hardware Mode A (CEN = 0), the COPY/C and ORIG pins

determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data stream,

see Table 2 on page 28. In Hardware Mode B, the COPY/C pin becomes the direct C bit input data pin,

which is sampled on both edges of LRCK.

EMPH

3

Pre-Emphasis Indicator (Input) - In Hardware Mode A (CEN = 0), the EMPHpin low sets the 3 empha-

sis channel status bits to indicate 50/15 s pre-emphasis of the transmitted audio data. If EMPH is high,

then the three EMPH channel status bits are set to 000, indicating no pre-emphasis.

AUDIO

19 Audio Channel Status Bit (

Input

) - In Hardware Mode A (CEN = 0), the AUDIO pin determines the

state of the audio/non audio Channel Status bit in the outgoing AES3 data stream.

ORIG

28

ORIG Channel Status Bit Control (Input) - In Hardware Mode A (CEN = 0), the ORIG and COPY/C

pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data

stream, see Table 2 on page 28.

TEST

2

7

8

Test Pins (Input) - These pins are unused inputs. It is recommended that these pins be tied to a supply

(VL or GND) to minimize leakage current. The CS8406 will operate correctly if these pins are left float-

ing, however current consumption from VL will increase by 25 A per TEST pin that is left floating.