28

DS580F6

CS8406

The channel status block pin (TCBL) may be an input or an output, determined by the state of the TCBLD

pin.

10.2 Serial Audio Port

The serial audio input port data format is selected as shown in Table 3, and may be set to master or slave

by the state of the APMS input pin. The OMCK clock ratio is selected as shown in Table 4. Table 5 describes

the equivalent Software Mode, bit se ttings for each of the available formats. Timing diagrams are shown in

Figure 7.

COPY/C

ORIG

Function

0

0

PRO=0, COPY=0, L=0 copyright

0

1

PRO=0, COPY=0, L=1 copyright, pre-recorded

1

0

PRO=0, COPY=1, L=0 non-copyright

11

PRO=1

Table 2. Hardware Mode COPY/C and ORIG Pin Functions

SFMT1 SFMT0

Function

0

0

Serial Input Format IF1 - Left Justified

0

1

Serial Input Format IF2 - I²S

1

0

Serial Input Format IF3 - Right-Justified, 24-bit data

1

1

Serial Input Format IF4 - Right-Justified, 16-bit data

Table 3. Hardware Mode Serial Audio Port Format Selection

HWCK1 HWCK0

Function

0

0

OMCK Frequency is 256*Fs

0

1

OMCK Frequency is 128*Fs

1

0

OMCK Frequency is 512*Fs

1

1

OMCK Frequency is 256*Fs

Table 4. Hardware Mode OMCK Clock Ratio Selection

SISF SIRES1/0 SIJUST SIDEL SISPOL SILRPOL

IF1 - Left Justified

0

00

0

0

0

0

IF2 - I²S

0

00

0

1

0

1

IF3 - Right-Justified, 24-bit data

0

00

1

0

0

0

IF4 - Right-Justified, 16-bit data

0

10

1

0

0

0

Table 5. Equivalent Register Settings of Serial Audio Input Formats in Hardware Mode