数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

CS8406-CSZ 数据表(PDF) 29 Page - Cirrus Logic

部件名 CS8406-CSZ
功能描述  192 kHz Digital Audio Interface Transmitter
PDF  39 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS8406-CSZ 数据表(HTML) 29 Page - Cirrus Logic

Back Button CS8406-CSZ Datasheet HTML 25Page - Cirrus Logic CS8406-CSZ Datasheet HTML 26Page - Cirrus Logic CS8406-CSZ Datasheet HTML 27Page - Cirrus Logic CS8406-CSZ Datasheet HTML 28Page - Cirrus Logic CS8406-CSZ Datasheet HTML 29Page - Cirrus Logic CS8406-CSZ Datasheet HTML 30Page - Cirrus Logic CS8406-CSZ Datasheet HTML 31Page - Cirrus Logic CS8406-CSZ Datasheet HTML 32Page - Cirrus Logic CS8406-CSZ Datasheet HTML 33Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 29 / 39 page
background image
DS580F6
29
CS8406
11.PIN DESCRIPTION - HARDWARE MODE
VD
6
Digital Power (Input) - Digital core power supply. Typically +3.3 V or +5.0 V.
VL
23
Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V.
GND
22
Ground (Input) - Ground for I/O and core logic.
RST
9
Reset (Input) - When RST is low, the CS8406 enters a low power mode and all internal states are reset.
On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable
in frequency and phase. This is particularly true in Hardware Mode with multiple CS8406 devices, where
synchronization between devices is important.
H/S
24
Hardware/Software Control Mode Select (Input) - Determines the method of controlling the operation
of the CS8406, and the method of accessing CS and U data. Hardware Mode provides an alternate
mode of operation, and access to CS and U data is provided by dedicated pins. To select Hardware
Mode, this pin should be permanently tied to VL.
TXN
TXP
25
26
Differential Line Drivers (Output) - These pins transmit biphase encoded data. The drivers are pulled
low while the CS8406 is in the reset state.
OMCK
21
Master Clock (Input) - The frequency can be set through the HWCK[1:0] pins.
ISCLK
13
Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin.
ILRCK
12 Serial Audio Input Left/Right Clock (
Input
/Output) - Word rate clock for the audio data on the SDIN
pin.
SDIN
14
Serial Audio Data Port (Input) - Audio data serial input pin.
COPY / C
ORIG
TEST
HWCK1
EMPH
TXP
SFMT0
TXN
SFMT1
H/S
VD
VL
TEST
GND
TEST
OMCK
RST
HWCK0
APMS
AUDIO
TCBLD
U
ILRCK
V
ISCLK
CEN
SDIN
TCBL
1
2
3
4
5
6
7
821
22
23
24
25
26
27
28
9
10
11
12
17
18
19
20
13
14
15
16



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com