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T89C5115-RATIM 数据表(PDF) 73 Page - ATMEL Corporation |
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T89C5115-RATIM 数据表(HTML) 73 Page - ATMEL Corporation |
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73 / 105 page  73 T89C5115 4128A–8051–04/02 PCA Registers Table 47. CMOD Register CMOD (S:D9h) PCA Counter Mode Register Reset Value = 00XX X000b 76 54 32 1 0 CIDL WDTE - - - CPS1 CPS0 ECF Bit Number Bit Mnemonic Description 7CIDL PCA Counter Idle Control bit Clear tolet thePCA runduringIdlemode. Set tostopthe PCA whenIdlemodeisinvoked. 6WDTE WatchDog Timer Enable Clear to disable WatchDog Timer function on PCA Module 4, Set to enable it. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2CPS1 EWC Count Pulse Select bits CPS1 CPS0 Clock Source 0 0 Internal Clock, FPca/6 0 1 Internal Clock, FPca/2 1 0 Timer 0 overflow 1 1 External clock at ECI/P1.2 pin (Max. Rate = FPca/4) 1CPS0 0ECF Enable PCA Counter Overflow Interrupt bit Clear to disable CF bit in CCON register to generate an interrupt. Set to enable CF bit in CCON register to generate an interrupt. |
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