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T89C5115-RATIM 数据表(PDF) 63 Page - ATMEL Corporation |
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T89C5115-RATIM 数据表(HTML) 63 Page - ATMEL Corporation |
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63 / 105 page ![]() 63 T89C5115 4128A–8051–04/02 WatchDog Programming The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration. Table 43. Machine Cycle Count To compute WD Time-Out, the following formula is applied: Note: Svalue represents the decimal value of (S2 S1 S0) The following table indicates the computed Time-Out value for Fosc XTAL =12 MHz in X1 mode Table 44. Time-Out Computation S2 S1 S0 Machine Cycle Count 000 214 -1 001 215 -1 010 216 -1 011 217 -1 100 218 -1 101 219 -1 110 220 -1 111 221 -1 S2 S1 S0 Fosc = 12 MHz Fosc = 16 MHz Fosc = 20 MHz 0 0 0 16.38 ms 12.28 ms 9.82 ms 0 0 1 32.77 ms 24.57 ms 19.66 ms 0 1 0 65.54 ms 49.14 ms 39.32 ms 0 1 1 131.07 ms 98.28 ms 78.64 ms 1 0 0 262.14ms 196.56ms 157.28ms 1 0 1 524.29ms 393.12ms 314.56ms 1 1 0 1.05sec 786.24ms 629.12ms 1 1 1 2.10 sec 1.57 s 1.25 ms FTime Out F wd 12 2 14 2 Svalue × () 1 – () × ------------------------------------------------------------------- = – |
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