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ADL5205ACPZ-R7 数据表(PDF) 15 Page - Analog Devices

部件名 ADL5205ACPZ-R7
功能描述  Dual, 35 dB Range, 1 dB Step Size DGA
PDF  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADL5205ACPZ-R7 数据表(HTML) 15 Page - Analog Devices

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ADL5205
Data Sheet
Rev. 0 | Page 14 of 31
0
–50
–30
–20
–10
–40
–35
–45
–25
–15
–5
250
–250
–50
50
150
–150
–100
–200
0
100
200
10
100
1k
FREQUENCY (MHz)
+26dB GAIN MAGNITUDE
–9dB GAIN MAGNITUDE
+26dB GAIN PHASE
–9dB GAIN PHASE
Figure 36. Differential Input Reflection (SDD11) Magnitude and Phase vs.
Frequency
–250
–200
–150
–100
–50
0
50
100
150
200
250
–3.0
–2.5
–4.0
–3.5
–5.0
–4.5
–2.0
–1.5
–1.0
–0.5
0
1000
FREQUENCY (MHz)
+26dB GAIN MAGNITUDE
–9dB GAIN MAGNITUDE
+26dB PHASE
–9dB PHASE
Figure 37. Differential Output Reflection (SDD22) Magnitude and Phase vs.
Frequency
12
0
8
4
6
2
10
1.2
–1.2
–0.4
–0.8
0
0.4
0.8
PROGRAMMED GAIN (dB)
–9
–6
–3
0
3
6
9
12
15
18
21
24 26
Figure 38. Phase Variation and Cumulative Gain Step Error vs. Programmed
Gain, Frequency = 200 MHz, VPOS = 3.3 V, 2 V p-p Composite
CH2 500mV/div 50Ω BW:8.0G
CH3 300mV/div 50Ω BW:5.0G
20.0ns/div
12.5GS/s
80.0ps/pt
A CH2
1.57V
3
2
T
Figure 39. Enable Time Domain Response at VPOS = 5 V
CH2 500mV/div 50Ω BW:8.0G
CH3 300mV/div 50Ω BW:5.0G
20.0ns/div
12.5GS/s
80.0ps/pt
A CH2
1.56V
3
2
T
Figure 40. Enable Time Domain Response at VPOS = 3.3 V
CH2 500mV/div 50Ω BW:8.0G
CH3 300mV/div 50Ω BW:5.0G
20.0ns/div
6.25GS/s
160ps/pt
A CH2
1.57V
3
2
T
Figure 41. Disable Time Domain Response at VPOS = 5 V



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