数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

ADL5205ACPZ-R7 数据表(PDF) 25 Page - Analog Devices

部件名 ADL5205ACPZ-R7
功能描述  Dual, 35 dB Range, 1 dB Step Size DGA
PDF  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADL5205ACPZ-R7 数据表(HTML) 25 Page - Analog Devices

Back Button ADL5205ACPZ-R7 Datasheet HTML 21Page - Analog Devices ADL5205ACPZ-R7 Datasheet HTML 22Page - Analog Devices ADL5205ACPZ-R7 Datasheet HTML 23Page - Analog Devices ADL5205ACPZ-R7 Datasheet HTML 24Page - Analog Devices ADL5205ACPZ-R7 Datasheet HTML 25Page - Analog Devices ADL5205ACPZ-R7 Datasheet HTML 26Page - Analog Devices ADL5205ACPZ-R7 Datasheet HTML 27Page - Analog Devices ADL5205ACPZ-R7 Datasheet HTML 28Page - Analog Devices ADL5205ACPZ-R7 Datasheet HTML 29Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 25 / 32 page
background image
ADL5205
Data Sheet
Rev. 0 | Page 24 of 31
PARALLEL INTERFACE
The functions of Parallel Interface Connector P3 are identical to
those of the switches in the switch block. The pinout of the
Parallel Interface Connector P3 is listed in Table 14. Logic levels
on the P3 pins override the corresponding switch setting. As a
result, the switches for PWUPA and PWUPB must be in the up
position when using the parallel interface to control the device.
Table 14. Parallel Interface Pinout (P3)
Pin Number
Function
1
PWUPB
2
AGND
3
LATCHB
4
AGND
5
B0
6
AGND
7
B1
8
AGND
9
B2
10
AGND
11
B3
12
AGND
13
B4
14
AGND
15
B5
16
AGND
17
VDD
18
AGND
19
Power mode (PM)
20
AGND
21
MODE0
22
AGND
23
MODE1
24
AGND
25
A5
26
AGND
27
A4
28
AGND
29
A3
30
AGND
31
A2
32
AGND
33
A1
34
AGND
35
A0
36
AGND
37
LATCHA
38
AGND
39
PWUPA
40
AGND
SERIAL INTERFACE
When the mode switches are in the 01 position, the ADL5205
operates in the serial/SPI mode. The pins that are relevant in the
serial/SPI mode are brought out to Serial Interface Connector P2.
The pinout for Serial Interface Connector P2 is listed in Table 15.
Note that only four pins (plus AGND) are used for the SPI, and
they include the following:
•
CSA and CSB are the active low serial port enable pins for
Channel A and Channel B, respectively.
•
SDIO is the serial data input and output line. SDIO is a
bidirectional pin.
•
SCLK is the serial clock pin.
For detailed operations and timing diagrams of the serial port
interface, see the Serial Peripheral Interface (SPI) section. These
signals operate at 3.3 V logic levels.
The CSA and CSB lines can be tied together to program both
channels at the same time.
Table 15. Serial Interface Connector (P2) Pinout
Pin Number
Function
1
PWUPA
2
Not applicable
3
FA_A
4
Not applicable
5
CSA
6
Not applicable
7
PM
8
Not applicable
9
SDIO
10
Not applicable
11
SCLK
12
Not applicable
13
CSB
14
Not applicable
15
FA_B
16
Not applicable
17
PWUPB
18
Not applicable
19
AGND
20
Not applicable



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com