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ADL5205ACPZ-R7 数据表(PDF) 19 Page - Analog Devices |
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ADL5205ACPZ-R7 数据表(HTML) 19 Page - Analog Devices |
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19 / 32 page ![]() ADL5205 Data Sheet Rev. 0 | Page 18 of 31 APPLICATIONS INFORMATION BASIC CONNECTIONS Figure 51 shows the basic connections for operating the ADL5205. Apply a voltage of 3.3 V or 5 V to the VPOS pins. Decouple each supply pin with at least one low inductance, surface-mount ceramic capacitor of 0.1 μF placed as close to the device as possible. The differential outputs have a dc common-mode voltage that is approximately half of the supply; therefore, decouple these outputs using 0.1 μF capacitors to the balanced load. The balanced differential inputs have the same dc common-mode voltage as the outputs; the inputs are decoupled using 0.1 μF capacitors as well. The digital pins, mode control pins, associated SPI pins, and parallel gain control pins, (PM, PWUPA, and PWUPB) operatefrom a 3.3 V voltage. To enable each channel of the ADL5205, pull the PWUPA pin or the PWUPB pin high (2.0 V ≤ PWUPA/PWUPB ≤ 3.3 V). A logic low on the PWUPA pin or the PWUPB pin sets the channel to sleep mode, reducing the current consumption to approximately 7 mA per channel. The VCMA and the VCMB pins are the reference inputs for the output common-mode voltage of each channel, and they must be decoupled with 0.1 μF capacitors. 3.3V 1 2 3 4 5 6 7 8 9 10 23 24 25 26 27 28 29 30 22 21 3.3V 3.3V 3.3V EXPOSED PAD BALANCED LOAD V POS ADL5205 BALANCED SOURCE AC 0.1µF 0.1µF 0.1µF 0.1µF 10µF 0.1µF BALANCED SOURCE AC 0.1µF 0.1µF 0.1µF CHANNEL B PARALLEL INTERFACE CHANNEL B PARALLEL INTERFACE 0.1µF 0.1µF BALANCED LOAD 0.1µF 0.1µF A4 A5 MODE1 MODE0 PM DNC SDIO/B5 SCLK/B4 CSA/A3 GS1/CSB/B3 DNC VPOS DNC DNC VPOS DNC VOUTB– VOUTB+ VOUTA+ VOUTA– NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS. 2. THE EXPOSED PAD MUST BE CONNECTED TO A LOW IMPEDANCE GROUND PLANE. THIS IS THE GROUND (0V) REFERENCE FOR ALL THE VOLTAGES IN TABLE 1. Figure 51. Basic Connections |
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