REFERENCE DESIGN

IRMCS2011

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9.3 Parallel Interface Port

IRMCS2011 provides an 8bit parallel interface port to facilitate microprocessor interface. Interface is generic and able

to interface most common 8bit parallel interface such as MCS8051, some Motorola 8bit uP, MicroChip, etc. Figure 16

shows the connection diagram. The connector, J5, is a 2-by-10 header connector pins.

Each signal is 3.3V level and data bus is multiplexed. Table 2 summarizes each signal definition.

NA

HP_Data7

HP_nOE

HP_nCS

NA

HP_Data5

HP_nWE

HP_Data0

NA

HP_Data3

HP_Data4

HP_Data2

HP_Data1

NA

HP_Data6

HP_A

J5

HDR2X10

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

+3.3V_BB

Figure 16. Parallel Interface Port, J9

Signal

I/O

1

Description

HP_nCS

I

Active low Host Port Chip Select

HP_nOE

I

Active Low Host Port Output Enable

HP_nWE

I

Active low Host Port Write Enable

HP_A

I

Host Port Register Address. 1 = Address register, 0 = Data Register

HP_Data

I/O

Bidirectional Host Port data bus

Table 2. Microprocessor Interface Module Signal Definitions

Figure 17 and Figure 18 show detailed timing requirements for register read and write operations depending on the

type of microprocessor (Intel or Motorola type).

All values are in nanoseconds. The data bus output is activated by

the logical combination (!nCS && !nOE && new), which allows read and write operations to be either nWe/nOE

(Intel) or nCS (Motorola) driven.