REFERENCE DESIGN

IRMCS2011

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21

Row

Name

Min

Max

Comment

1

C TsuADDR

10

HP_A to HPnCS or HP_nWE (which ever occurs last) low setup time

2

C TsuData

0

HP_D to HPnCS or HP_nWE (which ever occurs last) low setup time

3

C Tpw_nCSnWE

60

Minimum pulswidth for nCS and nWE

4

C ThData

60

Minimum data hold time from HP_nWE or HPnCS (whichever occurs last) low

5

C ThAddr

Minimum address hold time from HP_nWE or HPnCS (whichever occurs last) low

6

D Tacc

0

35

HP_nCS or HP_nOE (whichever occurs last) to Data access time

7

D ThData

0

35

HP_nCS or HP_nOE (whichever occurs last) to Data invalid/Hi-

TsuADDR

ThAddr

TsuData

Tpw_nCSnWE

ThData

Tpw_nCSnWE

Tacc

ThData

HP_A

HP_nCS

HP_nWE

HP_nOE

HP_DATA

Figure 17. Register Write/Read Timing (Intel)