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AD8233ACBZ-R7 数据表(PDF) 28 Page - Analog Devices |
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AD8233ACBZ-R7 数据表(HTML) 28 Page - Analog Devices |
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28 / 30 page ![]() Data Sheet AD8233 Rev. 0 | Page 27 of 29 The overall narrow-band nature of the two-pole, low-pass filter filter combination distorts the ECG waveform significantly. Therefore, it is only suitable to determine the heart rate, and not to analyze the ECG signal characteristics. The low-pass filter stage also includes a gain of 11, bringing the total system gain close to 1100. Because the ECG signal is measured at the hands, it is weaker than when measured closer to the heart. The RLD circuit drives to the third electrode, which can also be located at the hands, to cancel common-mode interference. HOLTER MONITOR CONFIGURATION The circuit in Figure 75 is designed for monitoring the shape of the ECG waveform. To obtain an ECG waveform with minimal distortion, the AD8233 is configured with a 0.5 Hz, single-pole, high-pass filter, followed by a two-pole, 40 Hz, low-pass filter. A third electrode is driven for optimum common-mode rejection. 70 0 0.01 1k FREQUENCY (Hz) 10 20 30 40 50 60 0.1 1 10 100 Figure 74. Frequency Response of Holter Monitor Circuit In addition to 40 Hz filtering, the op amp stage is configured for a gain of 2, resulting in a total system gain of 200. Keeping the gain lower helps with any motion artifacts picked up in band. To optimize the dynamic range of the system, the gain level is adjustable, depending on the input signal amplitude (which may vary with electrode placement) and ADC input range. RA LA RL +VS HPSENSE IAOUT +VS REFIN GND FR AC/DC SDN LOD +IN –IN HPDRIVE RLD RLDFB OUT OPAMP+ OPAMP– REFOUT SW AD8233 5.6nF 499kΩ 1MΩ 1MΩ 5.6nF 150kΩ 150kΩ 1MΩ 10MΩ 10MΩ 0.1µF 10MΩ 0.1µF 300kΩ 3.3µF +VS (= +2.5V) ELECTRODE INTERFACE ...TO 11-13 ENOB ADC RLD SDN 10MΩ +VS 1nF 10MΩ +VS 10MΩ ...TO MCU ...TO MCU 0.5Hz TO 40Hz GAIN = ×200 Figure 75. Holter Monitor Circuit |
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