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AD8233

Data Sheet

Rev. 0 | Page 18 of 29

RIGHT LEG DRIVE AMPLIFIER

The right leg drive (RLD) amplifier inverts the common-mode

signal that is present at the instrumentation amplifier inputs.

When the right leg drive output current is injected into the

subject, it counteracts common-mode voltage variations, thus

improving the common-mode rejection of the system.

The common-mode signal that is present across the inputs of

the instrumentation amplifier is derived from the transconduct-

ance amplifier, GM1. It is then connected to the inverting input

of A2 through a 150 kΩ resistor.

An integrator can be built by connecting a capacitor between the

RLD FB and RLD terminals. A good starting point is a 1 nF

capacitor, which places the crossover frequency at about 1 kHz

(the frequency at which the amplifier has an inverting unity gain).

This configuration results in about 26 dB of loop gain available

at a frequency range from 50 Hz to 60 Hz for common-mode line

rejection. Higher capacitor values reduce the crossover frequency,

thereby reducing the gain that is available for rejection and,

consequently, increasing the line noise. Lower capacitor values

move the crossover frequency to higher frequencies, allowing

increased gain. The tradeoff is that with higher gain, the system

can become unstable and saturate the output of the right leg

amplifier.

When using this amplifier to drive an electrode, place a resistor

in series with the output to limit the current to be always less

than 10 μA, even in fault conditions. For example, if the supply

used is 3.0 V, ensure that the resistor is greater than 330 kΩ to

account for component and supply variations.

RLD

1nF

*LIMIT CURRENT TO LESS THAN 10µA.

RLDFB

REFOUT

TO DRIVEN

ELECTRODE

150kΩ

VCM

Figure 51. Typical Configuration of Right-Leg Drive Circuit

In two electrode configurations, A2 can be shut down by setting

RLD SDN low for additional power savings. If left in shutdown,

it is recommended to leave both RLD and RLDFB floating.

Alternatively, RLD can be used to bias the inputs through

10 MΩ resistors as described in the Leads On/Off Detection

section. When the AD8233 is in shutdown and dc leads off

detection mode, RLD pulls down towards ground. This pull-

down acts as an LOD wake-up function, pulling the inputs

down when the electrodes are reconnected.

REFERENCE BUFFER

The AD8233 operates from a single supply. To simplify the

design of single-supply applications, the AD8233 includes a

reference buffer to create a virtual ground between the supply

voltage and the system ground. The signals present at the out-

put of the instrumentation amplifier are referenced around this

voltage. For example, if there is zero differential input voltage,

the voltage at the output of the instrumentation amplifier is this

reference voltage.

The reference voltage level is set at the REFIN pin. It can be set

with a voltage divider or by driving the REFIN pin from some

other point in the circuit (for example, from the ADC reference).

The voltage is available at the REFOUT pin for the filtering

circuits or for an ADC input.

REFIN

+VS

Figure 52. Setting the Internal Reference

To limit the power consumption of the voltage divider, the use

of large resistors is recommended, such as 10 MΩ. The designer

must keep in mind that high resistor values make it easier for

interfering signals to appear at the input of the reference buffer.

To minimize noise pickup, it is recommended to place the resistors

close to each other and as near as possible to the REFIN terminal.

Furthermore, use a capacitor in parallel with the lower resistor

on the divider for additional filtering, as shown in Figure 52.

Keep in mind that a large capacitor results in better noise

filtering but it takes longer to settle the reference after power-up.

The total time it takes the reference to settle within 1% can be

estimated with the formula

tSETTLE_REFERENCE =





Note that disabling the AD8233 with the shutdown terminal

does not discharge this capacitor.

FAST RESTORE CIRCUIT

Because of the low cutoff frequency used in high-pass filters in

ECG applications, signals may require several seconds to settle.

This settling time can result in a frustrating delay for the user

after a step response: for example, when the electrodes are first

connected.

This fast restore function is implemented internally, as shown in

Figure 53. The output of the instrumentation amplifier is connec-

ted to a window comparator. The window comparator detects a

saturation condition at the output of the instrumentation amplifier

when its voltage approaches 0.1 V from either supply rail.

SWITCH

TIMING

LOD

FR B3

IAOUT

0.1V

+IN

–IN

+VS – 0.1V

Figure 53. Fast Restore Circuit

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