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AD8233

Data Sheet

Rev. 0 | Page 20 of 29

AC Leads On/Off Detection

The ac leads off detection mode is useful when using two

electrodes. In this case, a conduction path must exist between

the two electrodes, which is usually formed by two resistors, as

shown in Figure 57.

These resistors also provide a path for bias return on each input.

Connect each resistor to REFOUT or RLD to maintain the inputs

within the common-mode range of the instrumentation

amplifier.

REFOUT

10MΩ

+VS

Figure 57. Circuit Configuration for Two Electrode AC Leads Off Detection

The AD8233 detects when an electrode is disconnected by

forcing a small 100 kHz current into the input terminals. This

current flows through the external resistors from IN+ to IN−

and develops a differential voltage across the inputs, which is

then synchronously detected and compared to an internal

threshold. The recommended value for these external resistors

is 10 MΩ. Low resistance values make the differential drop too

low to be detected and lower the input impedance of the amplifier.

When the electrodes are attached to the subject, the impedance

of this path must be less than 3 MΩ to maintain the drop below

the threshold of the comparator.

To use the ac leads off mode, tie the AC/DC pin to the positive

supply rail. Note that, whereas REFOUT is at a constant voltage

value, using the RLD output as the input bias may be more effective

in rejecting common-mode interference at the expense of

additional power.

In three electrode ac leads off detection mode, as shown in

Figure 58, pull-up resistors are not required, which improves

the input impedance of the circuit. This mode is beneficial for

dry electrode applications. The ac mode currents contribute 1/f

noise to the system; therefore, depending on the application, it

may be advantageous to use ac leads off detection as a spot check

and then switching to dc mode for improved ECG acquisition.

RLD

+VS

TO DRIVEN

ELECTRODE

Figure 58. Circuit Configuration for Three Electrode AC Leads Off Detection

The ac leads off detection mode continues to function in shutdown

mode as well. To keep the power under 1 μA, the clock is disabled

and the ac currents become dc currents. The current source on

+IN is 250 nA, while the current sink on –IN is −300 nA. The

stronger pull-down current on −IN acts as a wake-up function,

pulling LOD low when the electrodes are reconnected.

STANDBY OPERATION

The AD8233 includes a shutdown pin (SDN) that further

enhances the flexibility and ease of use in portable applications

where power consumption is critical. A logic level signal can be

applied to this pin to switch to shutdown mode, even when the

supply is still on.

Driving the SDN pin low places the AD8233 in shutdown mode

and draws less than 1 μA of supply current, offering considerable

power savings. To enter normal operation, drive SDN high;

when not using this feature, permanently tie SDN to +VS.

During shutdown operation, the AD8233 cannot maintain the

REFOUT voltage, but it does not drain the REFIN voltage,

thereby maintaining this additional conduction path from the

supply to ground.

When emerging from a shutdown condition, the charge stored

in the capacitors on the high-pass filters can saturate the instru-

mentation amplifier and subsequent stages. The use of the fast

restore feature helps reduce the recovery time and, therefore,

minimize on time in power sensitive applications.

Using leads on/off detection in shutdown mode allows system

level power saving. The microcontroller enters sleep mode

when the electrodes are disconnected, and the LOD signal acts

as an interrupt to wake up the microcontroller. An example of

this functionality is shown in Figure 59.

1 -

AT LEAST ONE ELECTRODE IS OFF

AND THEREFORE LOD OUTPUT IS HIGH.

MCU IS OFF AND SDN IS LOW.

(AD8233 SHUTDOWN CURRENT < 1µA)

2 -

LOD GOES LOW WHEN BOTH

ELECTRODES ARE CONNECTED.

A FALLING EDGE AT LOD WAKES UP

THE MCU.

3 -

MCU WAKES UP

AND SETS SDN HIGH.

4 -

AD8233 IS ACTIVE (~50µA)

AND MONITORING ECG.

250mV/DIV

400ms/DIV

OUT

SDN

LOD

Figure 59. Electrode Connection and System Wakeup Sequence

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