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WM8750LEFL/R 数据表(PDF) 13 Page - Wolfson Microelectronics plc

部件名 WM8750LEFL/R
功能描述  STEREO CODEC FOR PORTABLE AUDIO APPLICATIONS
PDF  56 Pages
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制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8750LEFL/R 数据表(HTML) 13 Page - Wolfson Microelectronics plc

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WM8750L
PP Rev 1.77 May 2003
13
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25
oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
ADCLRC/DACLRC propagation delay from BCLK falling edge
tDL
10
ns
ADCDAT propagation delay from BCLK falling edge
tDDA
10
ns
DACDAT setup time to BCLK rising edge
t
DST
10
ns
DACDAT hold time from BCLK rising edge
t
DHT
10
ns
AUDIO INTERFACE TIMING – SLAVE MODE
BCLK
DACLRC/
ADCLRC
t
BCH
t
BCL
t
BCY
DACDAT
ADCDAT
t
LRSU
t
DS
t
LRH
t
DH
t
DD
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25
oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
50
ns
BCLK pulse width high
tBCH
20
ns
BCLK pulse width low
tBCL
20
ns
ADCLRC/DACLRC set-up time to BCLK rising edge
tLRSU
10
ns
ADCLRC/DACLRC hold time from BCLK rising edge
tLRH
10
ns
DACDAT hold time from BCLK rising edge
t
DH
10
ns
ADCDAT propagation delay from BCLK falling edge
tDD
10
ns
Note:
BCLK period should always be greater than or equal to MCLK period.



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