WM8750LEFLSLASHR datasheet(37/56 Pages) WOLFSON

37 / 56 page

Product Preview

WM8750L

PP Rev 1.77 May 2003

AUDIO DATA FORMATS

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

BCLK

DACDAT/

ADCDAT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Input Word Length (WL)

Note: Input word length is defined by the WL register.

Timing is shown with LRP = 1

Figure 14 Left Justified Audio Interface (assuming n-bit word length)

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK

transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

BCLK

DACDAT/

ADCDAT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Input Word Length (WL)

Note: Input word length is defined by the WL register.

Timing is shown with LRP = 1

Figure 15 Right Justified Audio Interface (assuming n-bit word length)

In I

2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.

The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and

the MSB of the next.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

BCLK

DACDAT/

ADCDAT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

1 BCLK

Input Word Length (WL)

Note: Input word length is defined by the WL register.

Timing is shown with LRP = 1

Figure 16 I

2S Justified Audio Interface (assuming n-bit word length)

In DSP mode, the left channel MSB is available on either the 1

st (mode B) or 2nd (mode A) rising

edge of BCLK (selectable by LRP) following a rising edge of LRCLK. Right channel data immediately

WM8750LEFL/R 数据表(PDF) 37 Page - Wolfson Microelectronics plc

WM8750LEFL/R 数据表(HTML) 37 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表下载

链接网址

WM8750LEFL/R 数据表(PDF) 37 Page - Wolfson Microelectronics plc

WM8750LEFL/R 数据表(HTML) 37 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表 下载

链接网址

数据表下载