| 数据搜索系统,热门电子元器件搜索 |
|
WM8750LEFL/R 数据表(PDF) 36 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8750LEFL/R 数据表(HTML) 36 Page - Wolfson Microelectronics plc |
|
36 / 56 page ![]() WM8750L Product Preview PP Rev 1.77 May 2003 36 LINE OUTPUT The analogue outputs, LOUT1/ROUT1 and LOUT2/ROUT2, can be used as line outputs. Additionally, OUT3 and MONOOUT can be used as a stereo line-out by setting OUT3SW=11 (reg. 24) and ensuring the contents of registers 38 and 39 (mono-out mix) are the same as reg. 34 and 35 (left out mix). Recommended external components are shown below. AGND AGND LINE-OUT SOCKET (LEFT) C1 1uF R1 100 Ohm LOUT1/2 or OUT3 (OUT3SW=11) ROUT1/2 or MONOOUT WM8750L R2 100 Ohm LINE-OUT SOCKET (RIGHT) C2 1uF Figure 11 Recommended Circuit for Line Output The DC blocking capacitors and the load resistance together determine the lower cut-off frequency, f c. Assuming a 10 kOhm load and C1, C2 = 1µF: f c = 1 / 2π (RL+R1) C1 = 1 / (2π x 10.1kΩ x 1µF) = 16 Hz Increasing the capacitance lowers f c, improving the bass response. Smaller values of C1 and C2 will diminish the bass response. The function of R1 and R2 is to protect the line outputs from damage when used improperly. DIGITAL AUDIO INTERFACE The digital audio interface is used for inputting DAC data into the WM8750L and outputting ADC data from it. It uses five pins: • ADCDAT: ADC data output • ADCLRC: ADC data alignment clock • DACDAT: DAC data input • ADCLRC: DAC data alignment clock • BCLK: Bit clock, for synchronisation The clock signals BCLK, ADCLRC and DACLRC can be outputs when the WM8750L operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). Four different audio data formats are supported: • Left justified • Right justified • I 2S • DSP mode All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for timing information. MASTER AND SLAVE MODE OPERATION The WM8750L can be configured as either a master or slave mode device. As a master device the WM8750L generates BCLK, ADCLRC and DACLRC and thus controls sequencing of the data transfer on ADCDAT and DACDAT. In slave mode, the WM8750L responds with data to clocks it receives over the digital audio interface. The mode can be selected by writing to the MS bit (see Table 23). Master and slave modes are illustrated below. BCLK ADCDAT ADCLRC DACDAT DACLRC WM8750 CODEC DSP ENCODER/ DECODER Note: The ADC and DAC can run at different sample rates BCLK ADCDAT ADCLRC DACDAT DACLRC WM8750 CODEC DSP ENCODER/ DECODER Note: The ADC and DAC can run at different sample rates Figure 12 Master Mode Figure 13 Slave Mode |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |