DA14581_16 datasheet(8/153 Pages) DIALOG

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Datasheet

Revision 3.2

17-Jan-2017

CFR0011-120-01

8 of 153

DA14581

Bluetooth Low Energy 4.2 SoC with Optimized Boot Time

FINAL

System Overview

The DA14581 contains the following internal blocks:

4.1 ARM CORTEX

M0 CPU

The Cortex-M0 processor is a 32-bit Reduced Instruc-

tion Set Computing (RISC) processor with a von Neu-

mann architecture (single bus interface). It uses an

instruction set called Thumb, which was first supported

in the ARM7TDMI processor; however, several newer

instructions from the ARMv6 architecture and a few

instructions from the Thumb-2 technology are also

included. Thumb-2 technology extended the previous

Thumb instruction set to allow all operations to be car-

ried out in one CPU state. The instruction set in

Thumb-2 includes both 16-bit and 32-bit instructions;

most instructions generated by the C compiler use the

16-bit instructions, and the 32-bit instructions are used

when the 16-bit version cannot carry out the required

operations. This results in high code density and

avoids the overhead of switching between two instruc-

tion sets.

In total, the Cortex-M0 processor supports only 56

base instructions, although some instructions can have

more than one form. Although the instruction set is

small, the Cortex-M0 processor is highly capable

because the Thumb instruction set is highly optimized.

Academically, the Cortex-M0 processor is classified as

load-store architecture, as it has separate instructions

for reading and writing to memory, and instructions for

arithmetic or logical operations that use registers.

Features

• Thumb instruction set. Highly efficient, high code

density and able to execute all Thumb instructions

from the ARM7TDMI processor.

• High performance. Up to 0.9 DMIPS/MHz (Dhrys-

tone 2.1) with fast multiplier.

• Built-in Nested Vectored Interrupt Controller (NVIC).

This makes interrupt configuration and coding of

exception handlers easy. When an interrupt request

is taken, the corresponding interrupt handler is exe-

cuted automatically without the need to determine

the exception vector in software.

• Interrupts can have four different programmable pri-

ority levels. The NVIC automatically handles nested

interrupts.

• The design is configured to respond to exceptions

(e.g. interrupts) as soon as possible (minimum 16

clock cycles).

• Non maskable interrupt (NMI) input for safety critical

systems.

• Easy to use and C friendly. There are only two

modes (Thread mode and Handler mode). The

whole application, including exception handlers, can

be written in C without any assembler.

• Built-in System Tick timer for OS support. A 24-bit

timer with a dedicated exception type is included in

the architecture, which the OS can use as a tick

timer or as a general timer in other applications with-

out an OS.

• SuperVisor Call (SVC) instruction with a dedicated

SVC exception and PendSV (Pendable SuperVisor

service) to support various operations in an embed-

ded OS.

• Architecturally defined sleep modes and instructions

to enter sleep. The sleep features allow power con-

sumption to be reduced dramatically. Defining sleep

modes as an architectural feature makes porting of

software easier because sleep is entered by a spe-

cific instruction rather than implementation defined

control registers.

• Fault handling exception to catch various sources of

errors in the system.

• Support for 24 interrupts.

• Little endian memory support.

• Wake up Interrupt Controller (WIC) to allow the pro-

cessor to be powered down during sleep, while still

allowing interrupt sources to wake up the system.

• Halt mode debug. Allows the processor activity to

stop completely so that register values can be

accessed and modified. No overhead in code size

and stack memory size.

• CoreSight technology. Allows memories and periph-

erals to be accessed from the debugger without halt-

ing the processor.

• Supports Serial Wire Debug (SWD) connections.

The serial wire debug protocol can handle the same

debug features as the JTAG, but it only requires two

wires and is already supported by a number of

debug solutions from various tools vendors.

• Four (4) hardware breakpoints and two (2) watch

points.

• Breakpoint instruction support for an unlimited num-

ber of software breakpoints.

• Programmer’s model similar to the ARM7TDMI pro-

cessor. Most existing Thumb code for the

ARM7TDMI processor can be reused. This also

makes it easy for ARM7TDMI users, as there is no

need to learn a new instruction set.

4.2 BLUETOOTH LOW ENERGY

4.2.1 BLE Core

The BLE (Bluetooth low energy) core is a qualified

Bluetooth baseband controller compatible with the

Bluetooth low energy 4.2 specification and it is in

charge of packet encoding/decoding and frame sched-

uling.

Features

• All device classes support (Broadcaster, Central,

Observer, Peripheral)

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