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DA14581 数据表(PDF) 28 Page - Dialog Semiconductor |
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DA14581 数据表(HTML) 28 Page - Dialog Semiconductor |
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28 / 153 page ![]() Datasheet Revision 3.2 17-Jan-2017 CFR0011-120-01 28 of 153 © 2014 Dialog Semiconductor DA14581 Bluetooth Low Energy 4.2 SoC with Optimized Boot Time FINAL Table 16: CLK_RADIO_REG (0x50000008) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7 r/w BLE_ENABLE Enable the BLE core clocks 0x0 6 r/w BLE_LP_RESET Reset for the BLE LP timer 0x1 5:4 r/w BLE_DIV Division factor for BLE core blocks 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 The programmed frequency should not be lower than 8 MHz and not faster than the programmed CPU clock frequency. Refer also to BLE_CNTL2_REG[BLE_CLK_SEL]. 0x0 3 r/w RFCU_ENABLE Enable the RF control Unit clock 0x0 2 - - Reserved 0x0 1:0 r/w RFCU_DIV Division factor for RF Control Unit 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 The programmed frequency must be exactly 8 MHz. 0x0 Table 17: CLK_CTRL_REG (0x5000000A) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7 r RUNNING_AT_XTAL 16M Indicates that the XTAL16M clock is used as clock, and may not be switched off 0x1 6 r RUNNING_AT_RC16 M Indicates that the RC16M clock is used as clock 0x0 5 r RUNNING_AT_32K Indicates that either the RC32k or XTAL32k is being used as clock 0x0 4 - - Reserved 0x0 3 r/w XTAL16M_SPIKE_FL T_DISABLE Disable spikefilter in digital clock 0x0 2 r/w XTAL16M_DISABLE Setting this bit instantaneously disables the 16 MHz crystal oscillator. Also, after sleep/wakeup cycle, the oscillator will not be enabled. This bit may not be set to '1'when "RUNNING_AT_XTAL16M is '1' to prevent deadlock. After resetting this bit, wait for XTAL16_SETTLED or XTAL16_TRIM_READY to become '1' before switching to XTAL16 clock source. 0x0 1:0 r/w SYS_CLK_SEL Selects the clock source. 0x0: XTAL16M (check the XTAL16_SETTLED and XTAL16_TRIM_READY bits!!) 0x1: RC16M 0x2/0x3: either RC32k or XTAL32k is used 0x0 Table 18: PMU_CTRL_REG (0x50000010) Bit Mode Symbol Description Reset 15:12 - - Reserved 0x0 |
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