DA14581_16 datasheet(10/153 Pages) DIALOG

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Datasheet

Revision 3.2

17-Jan-2017

CFR0011-120-01

10 of 153

DA14581

Bluetooth Low Energy 4.2 SoC with Optimized Boot Time

FINAL

Core drivers are provided for each interface of the

DA14580 enabling optimized usage of the hardware’s

capabilities. These drivers provide an easy-to-use

interface towards the hardware engines without having

to interfere with the register programming directly.

On top of the core drivers, a number of sample drivers

is also provided enabling communication with basic

Bluetooth Smart application components: accelerome-

ters, FLASH/EEPROM non-volatile memories, etc.

4.3 MEMORIES

The following memories are part of the DA14580’s

internal blocks:

ROM. This is a 84 kB ROM containing the Bluetooth

low energy protocol stack as well as the boot code

sequence.

OTP. This is a 32 kB One-Time Programmable memory

array, used to store the application code as well as

Bluetooth low energy profiles. It also contains the sys-

tem configuration and calibration data.

System SRAM. This is a 42 kB system SRAM (Sys-

RAM) which is primarily used for mirroring the program

code from the OTP when the system wakes/powers

up. It also serves as Data RAM for intermediate vari-

ables and various data that the protocol requires.

Optionally, it can be used as extra memory space for

the BLE TX and RX data structures.

Retention RAMs. These are 4 special low leakage

SRAM cells (2 kB + 2 kB + 3 kB + 1 kB) used to store

various data of the Bluetooth low energy protocol as

well as the system’s global variables and processor

stack when the system goes into Deep Sleep mode.

Storage of this data ensures secure and quick configu-

ration of the BLE Core after the system wakes up.

Every cell can be powered on or off according to the

application needs for retention area when in Deep

Sleep mode.

4.4 FUNCTIONAL MODES

The DA14581 is optimized for deeply embedded appli-

cations such as health monitoring, sports measuring,

human interaction devices etc. Customers are able to

develop and test their own applications. Upon comple-

tion of the development, the application code can be

programmed into the OTP. In general, the system has

three functional modes of operation:

A. Development Mode: During this phase application

code is developed using the ARM Cortex-M0 SW envi-

ronment. The compiled code is then downloaded into

the System RAM or any Retention RAMs by means of

SWD (JTAG) or any serial interface (e.g. UART).

Address 0x00 is remapped to the physical memory that

contains the code and the CPU is configured to reset

and execute code from the remapped device. This

mode is enabling application development, debugging

and on-the-fly testing.

B. Normal Mode: After the application is ready and

verified, the code can be burned into the OTP. When

the system boots/wakes up, the DMA of the OTP con-

troller will automatically copy the program code from

the OTP into the system RAM. Next, a SW reset or a

jump to the System RAM occurs and code execution is

started. Hence, in this mode, the system is autono-

mous, contains the required SW in OTP and is ready

for integration into the final product.

C. Calibration Mode: Between Development and Nor-

mal mode, there is an intermediate stage where the

chip needs to be calibrated with respect to two impor-

tant features:

• Programming of the Bluetooth device address

• Programming of the trimming value for the external

16 MHz crystal.

Figure 5: Hardware Abstraction Layer

GPIO

Driver

Application

Accelerometer

Driver

SPI

Driver

UART

Driver

SPI FLASH

Driver

ADC

Driver

Battery

Driver

Quadrature

EEPROM

I2C

Driver

Sample

Drivers

CORE

Drivers

Timers

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