8

Am29F032B

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register it-

self does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function of

the device. The appropriate device bus operations

table lists the inputs and control levels required, and the

resulting output. The following subsections describe

each of these operations in further detail.

Table 1.

Am29F032B Device Bus Operations

Legend:

L = Logic Low = V

Note: See the sections Sector Group Protection and Temporary Sector Unprotect for more information.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to V

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at V

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. The device remains

enabled for read access until the command register

contents are altered.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to the Read Operations Timings diagram for

the timing waveforms. I

table represents the active current specification for

reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V

An erase operation can erase one sector, multiple sec-

tors, or the entire device. The Sector Address Tables

indicate the address space that each sector occupies.

A “sector address” consists of the address bits re-

quired to uniquely select a sector. See the “Writing

specific address and data commands or sequences

into the command register initiates device operations.

The Command Definitions table defines the valid reg-

ister command sequences. Writing incorrect address

and data values or writing them in the improper se-

quence resets the device to reading array data.” sec-

tion for details on erasing a sector or the entire chip, or

suspending/resuming the erase operation.

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to the “Autoselect Mode” and “Au-

toselect Command Sequence” sections for more infor-

mation.

I

tive current specification for the write mode. The “AC

Operation

CE#

OE#

WE#

RESET#

A0–A21

DQ0–DQ7

Read

L

L

H

H

A

IN

D

OUT

Write

L

H

L

H

A

IN

D

IN

CMOS Standby

V

X

X

V

X

High-Z

TTL Standby

H

X

X

H

X

High-Z

Output Disable

L

H

H

H

X

High-Z

Hardware Reset

X

X

X

L

X

High-Z

Temporary Sector Unprotect

(See Note)

XX

X

V

ID

A

IN

D

IN