MPC8240 datasheet(2/52 Pages) MOTOROLA

2 / 52 page

MPC8240 Integrated Processor Hardware Specifications

MOTOROLA

Overview

Figure 1. MPC8240 Block Diagram

The peripheral logic integrates a PCI bridge, memory controller, DMA controller, PIC interrupt controller,

I2O controller, and an I

2C controller. The MPC603e core is a full-featured, high-performance processor with

floating-point support, memory management, a 16-Kbyte instruction cache, a 16-Kbyte data cache, and

Peripheral Logic Bus

Instruction Unit

System

Integer

Load/Store

Floating-

Address

Translator

DLL

Fanout

Buffers

PCI

Arbiter

Data

Instruction

16-Kbyte

Message

Unit

(with I2O)

I2C

Controller

DMA

Controller

Interrupt

Controller/

PIC

Timers

PCI Bus

Interface Unit

Memory

Controller

Data Path

ECC Controller

Central

Control

Unit

32-Bit

OSC In

Five

Request/Grant

Pairs

I2C

5 IRQs/

Processor Core Block

Peripheral Logic Block

Processor

PLL

(64-Bit) Two-Instruction Fetch

(64-Bit) Two-Instruction Dispatch

Peripheral Logic

PLL

SDRAM Clocks

PCI Clock In

PCI Bus Clocks

Data (64-Bit)

Address

Data Bus

DRAM/SDRAM/

Address/Control

64-Bit

PCI Interface

16 Serial

Interrupts

Branch

Processing

Unit

(BPU)

MPC8240

Configuration

Registers

Unit

(SRU)

Unit

(IU)

Unit

(LSU)

Point

Unit

(FPU)

(32-Bit)

Data

Cache

Instruction

Cache

MMU

Additional Features:

• Prog I/O with Watchpoint

• JTAG/COP Interface

• Power Management

with 8-Bit Parity

or ECC

SDRAM Sync Out

SDRAM Sync In

ROM/Flash/Port X

(32- or 64-Bit)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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