MPC8240 datasheet(3/52 Pages) MOTOROLA

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MPC8240 Integrated Processor Hardware Specifications

Features

power management features. The integration reduces the overall packaging requirements and the number of

discrete devices required for an embedded system.

The MPC8240 contains an internal peripheral logic bus that interfaces the MPC603e core to the peripheral

logic. The core can operate at a variety of frequencies, allowing the designer to trade off performance for

power consumption. The MPC603e core is clocked from a separate PLL, which is referenced to the

peripheral logic PLL. This allows the microprocessor and the peripheral logic block to operate at different

frequencies while maintaining a synchronous bus interface. The interface uses a 64- or 32-bit data bus

(depending on memory data bus width) and a 32-bit address bus along with control signals that enable the

interface between the processor and peripheral logic to be optimized for performance. PCI accesses to the

MPC8240 memory space are passed to the processor bus for snooping purposes when snoop mode is

enabled.

The MPC8240 features serve a variety of embedded applications. In this way, the MPC603e core and

peripheral logic remain general-purpose. The MPC8240 can be used as either a PCI host or an agent

controller.

1.2

Features

This section summarizes features of the MPC8240. Major features of the MPC8240 are as follows:

•

Peripheral logic

— Memory interface

– Programmable timing supporting either FPM DRAM, EDO DRAM, or SDRAM

– High-bandwidth bus (32- or 64-bit data bus) to DRAM

– Supports one to eight banks of 4-, 16-, 64-, or 128-Mbit memory devices

– Supports 1-Mbyte to 1-Gbyte DRAM memory

– 16 Mbytes of ROM space

– 8-, 32-, or 64-bit ROM

– Write buffering for PCI and processor accesses

– Supports normal parity, read-modify-write (RMW), or ECC

– Data-path buffering between memory interface and processor

– Low-voltage TTL logic (LVTTL) interfaces

– Port X: 8-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with

programmable address strobe timing

— 32-bit PCI interface operating up to 66 MHz

– PCI 2.1-compliant

– PCI 5.0-V tolerance

– Support for PCI locked accesses to memory

– Support for accesses to PCI memory, I/O, and configuration spaces

– Selectable big- or little-endian operation

– Store gathering of processor-to-PCI write and PCI-to-memory write accesses

– Memory prefetching of PCI read accesses

– Selectable hardware-enforced coherency

– PCI bus arbitration unit (five request/grant pairs)

– PCI agent mode capability

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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