STM32F411CC datasheet(147/149 Pages) STMICROELECTRONICS

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STM32F411xC STM32F411xE

Revision history

148

Revision history

Table 88. Document revision history

Date

Revision

Changes

19-Jun-2014

Initial release.

10-Sep-2014

Introduced the BAM feature in Features, Section 2: Description., and Section 3.3: Batch

Acquisition mode (BAM).

Updated Section 3.5: Embedded Flash memory, Section 3.14: Power supply schemes

and Section 3.18: Low-power modes, Section 3.20.2: General-purpose timers (TIMx)

and Section 3.30: Temperature sensor.

Modified Table 8: STM32F411xC/xE pin definitions, Table 9: Alternate function mapping

and APB2 in Table 10: STM32F411xC/xE register boundary addresses.

Modified Table 34: Low-power mode wakeup timings(1), Table 20: Typical and

maximum current consumption, code with data processing (ART accelerator disabled)

running from SRAM - VDD = 1.7 V, Table 21: Typical and maximum current

consumption, code with data processing (ART accelerator disabled) running from

SRAM - VDD = 3.6 V, Table 25: Typical and maximum current consumption in run mode,

code with data processing (ART accelerator enabled with prefetch) running from Flash

memory - VDD = 3.6 V, Table 26: Typical and maximum current consumption in Sleep

mode - VDD = 3.6 V and Table 58: I2C characteristics and Figure 33: I2C bus AC

waveforms and measurement circuit.

Added Figure 21: Low-power mode wakeup, Section Appendix A: Recommendations

when using the internal reset OFF and Section Appendix B: Application block diagrams.

27-Nov-2014

Changed datasheet status to Production Data.

Updated Table 31: Typical and maximum current consumptions in VBAT mode.

Section : On-chip peripheral current consumption: changed HCLK frequency and

updated DMA1 and DMA2 current consumption in Table 33: Peripheral current

consumption.

Updated Table 55: I/O AC characteristics.

Updated THD in Table 69: ADC dynamic accuracy at fADC = 18 MHz - limited test

conditions and Table 70: ADC dynamic accuracy at fADC = 36 MHz - limited test

conditions.

Updated Table 55: I/O AC characteristics.

Updated Figure 46: WLCSP49 - 49-ball, 2.999 x 3.185 mm, 0.4 mm pitch wafer level

chip scale package outline and Figure 48: WLCSP49 marking (package top view).

Added Figure 47: WLCSP49 - 49-ball, 2.999 x 3.185 mm, 0.4 mm pitch wafer level chip

scale recommended footprint and Table 80: WLCSP49 recommended PCB design

rules (0.4 mm pitch).

Updated Figure 51: UFQFPN48 marking example (package top view), Figure 54:

LQFP64 marking example (package top view), Figure 57: LQPF100 marking example

(package top view), and Figure 58: UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch,

ultra fine pitch ball grid array package outline.

04-Feb-2015

Added VPP alternate function for BOOT0 in Table 8: STM32F411xC/xE pin definitions.

Added TC inputs in Table 11: Voltage characteristics, Table 12: Current characteristics,

Table 14: General operating conditions,

Table 53: I/O static characteristics and

Figure 30: FT/TC I/O input characteristics.

Updated VESD(CDM) in Table 50: ESD absolute maximum ratings.

A3 minimum and maximum values removed in Table 83: UFBGA100 - 100-ball, 7 x 7

mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data.

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