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OMAP3530ECBBA 数据表(PDF) 205 Page - Texas Instruments

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部件名 OMAP3530ECBBA
功能描述  Applications Processors
PDF  265 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OMAP3530ECBBA 数据表(HTML) 205 Page - Texas Instruments

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OMAP3530, OMAP3525
www.ti.com
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
Table 6-50. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Rising Edge and Transmit Mode(1)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B5
tsu(FSXV-CLKXAE)
Setup time, mcbspx_fsx valid before mcbspx_clkx
3.7
7.9
ns
active edge
B6
th(CLKXAE-FSXV)
Hold time, mcbspx_fsx valid after mcbspx_clkx active
0.5
0.5
ns
edge
(1)
In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode
on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).
Table 6-51. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Rising Edge and Transmit
Mode(1)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B2
td(CLKXAE-FSXV)
Delay time, mcbspx_clkx active edge to mcbspx_fsx
0.7
14.8
0.7
29.6
ns
valid
B8
td(CLKXAE-DXV)
Delay time, mcbspx_clkx active edge to
Master
0.6
14.8
0.6
29.6
ns
mcbspx_dx valid
Slave
0.6
14.8
0.6
29.6
ns
(1)
In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode
on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).
Table 6-52. McBSP4 (Set #1) Timing Requirements – Rising Edge and Transmit Mode(1)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B5
tsu(FSXV-CLKXAE)
Setup time, mcbspx_fsx valid before mcbspx_clkx
3.7
7.9
ns
active edge
B6
th(CLKXAE-FSXV)
Hold time, mcbspx_fsx valid after mcbspx_clkx active
0.5
0.5
ns
edge
(1)
In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-54.
Table 6-53. McBSP4 (Set #1) Switching Characteristics – Rising Edge and Transmit Mode(1)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B2
td(CLKXAE-FSXV)
Delay time, mcbspx_clkx active edge to
0.7
16.6
0.7
33.1
ns
mcbspx_fsx valid
B8
td(CLKXAE-DXV)
Delay time, mcbspx_clkx active edge
Master
0.6
16.6
0.6
33.1
ns
to mcbspx_dx valid
Slave
0.6
17.3
0.6
33.1
ns
(1)
In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-54.
Table 6-54. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Rising Edge and Transmit Mode(1)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B5
tsu(FSXV-CLKXAE)
Setup time, mcbspx_fsx valid before mcbspx_clkx
5.8
12.2
ns
active edge
B6
th(CLKXAE-FSXV)
Hold time, mcbspx_fsx valid after mcbspx_clkx active
0.5
0.5
ns
edge
(1)
In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-54.
Copyright © 2008–2013, Texas Instruments Incorporated
TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
205
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