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OMAP3530ECBBA 数据表(PDF) 209 Page - Texas Instruments |
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OMAP3530ECBBA 数据表(HTML) 209 Page - Texas Instruments |
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209 / 265 page  mcbspx_clkx mcbspx_fsx mcbspx_dx D7 D6 D5 B2 B2 B8 030-074 OMAP3530, OMAP3525 www.ti.com SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013 Table 6-64. McBSP4 (Set #1) Timing Requirements – Falling Edge and Transmit Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B5 tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before 3.7 7.9 ns mcbspx_clkx active edge B6 th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx 0.5 0.5 ns active edge (1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-66. Table 6-65. McBSP4 (Set #1) Switching Characteristics – Falling Edge and Transmit Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 16.6 0.7 33.1 ns valid B8 td(CLKXAE-DXV) Delay time, mcbspx_clkx active edge to Master 0.6 16.6 0.6 33.1 ns mcbspx_dx valid Slave 0.6 17.3 0.6 33.1 ns (1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-66. Table 6-66. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Falling Edge and Transmit Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B5 tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx 5.8 12.2 ns active edge B6 th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx 0.5 0.5 ns active edge (1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are specified in Table 6-66. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins). Table 6-67. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Falling Edge and Transmit Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx valid 0.7 22.2 0.7 44.4 ns B8 td(CLKXAE-DXV) Delay time, mcbspx_clkx active edge to Master 0.6 22.2 0.6 44.4 ns mcbspx_dx valid Slave 0.6 22.2 0.6 44.4 ns (1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are specified in Table 6-66. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins). Figure 6-39. McBSP Falling Edge Transmit Timing in Master Mode Copyright © 2008–2013, Texas Instruments Incorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 209 Submit Documentation Feedback Product Folder Links: OMAP3530 OMAP3525 |
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