OMAP3530ECBBA datasheet(211/265 Pages) TI1

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OMAP3530, OMAP3525

www.ti.com

SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013

6.6.2

Multichannel Serial Port Interface (McSPI) Timing

The multichannel SPI is a master/slave synchronous serial bus. The McSPI1 module supports up to four

peripherals and the others (McSPI2, McSPI3, and McSPI4) support up to two peripherals. The following

timings are applicable to the different configurations of McSPI in master/slave mode for any McSPI and

any channel (n).

6.6.2.1

McSPI in Slave Mode

Table 6-71 and Table 6-72 assume testing over the recommended operating conditions (see Figure 6-41).

Table 6-71. McSPI Interface Timing Requirements – Slave Mode(1) (2)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

1/SS

1/tc(CLK)

Frequency, mcspix_clk

MHz

tj(CLK)

Cycle jitter(3), mcspix_clk

-200

200

-200

200

SS1

tw(CLK)

Pulse duration, mcspix_clk high or low

0.45*P(4)

0.55*P(4)

0.45*P(4)

0.55*P(4)

SS2

tsu(SIMOV-CLKAE)

Setup time, mcspix_simo valid before mcspix_clk

4.2

9.5

active edge

SS3

th(SIMOV-CLKAE)

Hold time, mcspix_simo valid after mcspix_clk active

4.6

9.9

edge

SS4

tsu(CS0V-CLKFE)

Setup time, mcspix_cs0 valid before mcspix_clk first

13.8

28.6

edge

SS5

th(CS0I-CLKLE)

Hold time, mcspix_cs0 invalid after mcspix_clk last

13.8

28.6

edge

(1)

The input timing requirements are given by considering a rise time and a fall time of 4 ns.

(2)

In mcspix, x is equal to 1, 2, 3, or 4.

(3)

Maximum cycle jitter supported by mcspix_clk input clock.

(4)

P = mcspix_clk clock period

Table 6-72. McSPI Interface Switching Requirements(1) (2) (3) (4)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

SS6

td(CLKAE-SOMIV)

Delay time, mcspix_clk active edge to mcspix_somi

1.8

15.9

3.2

31.7

shifted

SS7

td(CS0AE-SOMIV)

Delay time, mcspix_cs0 active edge to

Modes 0 and 2

15.9

31.7

mcspix_somi shifted

(1)

The capacitive load is equivalent to 20 pF.

(2)

In mcspix, x is equal to 1, 2, 3, or 4.

(3)

The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all

software configurable.

(4)

This timing applies to all configurations regardless of mcspix_clk polarity and which clock edges are used to drive output data and

capture input data.

TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

211

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