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OMAP3530ECBBA 数据表(PDF) 208 Page - Texas Instruments |
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OMAP3530ECBBA 数据表(HTML) 208 Page - Texas Instruments |
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208 / 265 page  mcbspx_clkr mcbspx_fsr mcbspx_dr D7 D6 D5 B3 B4 B5 B6 030-073 mcbspx_clkr mcbspx_fsr mcbspx_dr D7 D6 D5 B2 B2 B3 B4 030-072 OMAP3530, OMAP3525 SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013 www.ti.com Table 6-61. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Falling Edge and Receive Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 22.2 0.7 44.4 ns valid (1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are specified in the table above. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins). Figure 6-37. McBSP Falling Edge Receive Timing in Master Mode Figure 6-38. McBSP Falling Edge Receive Timing in Slave Mode 6.6.1.1.4 Transmit Timing with Falling Edge as Activation Edge Table 6-62 through Table 6-67 assume testing over the recommended operating conditions (see Figure 6- 39 and Figure 6-40). Table 6-62. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Falling Edge and Transmit Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B5 tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx 3.7 7.9 ns active edge B6 th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx 0.5 0.5 ns active edge (1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode on UART pins) and Set #3 (multiplexing mode on McBSP1 pins). Table 6-63. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Falling Edge and Transmit Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 14.8 0.7 29.6 ns valid B8 td(CLKXAE-DXV) Delay time, mcbspx_clkx active edge to Master 0.6 14.8 0.6 29.6 ns mcbspx_dx valid Slave 0.6 14.8 0.6 29.6 ns (1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode on UART pins) and Set #3 (multiplexing mode on McBSP1 pins). 208 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OMAP3530 OMAP3525 |
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