SC16C752B datasheet(5/47 Pages) PHILIPS

5 / 47 page

Philips Semiconductors

SC16C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Product data

Rev. 03 — 14 December 2004

5 of 47

9397 750 14443

5.2 Pin description

Table 2:

Pin description

Symbol

Type

Description

LQFP48 HVQFN32

Address 0 select bit. Internal registers address selection.

Address 1 select bit. Internal registers address selection.

Address 2 select bit. Internal registers address selection.

CDA, CDB

40, 16

Carrier Detect (Active-LOW). These inputs are associated with individual

UART channels A and B. A logic LOW on these pins indicates that a carrier

has been detected by the modem for that channel. The state of these inputs

is reﬂected in the modem status register (MSR).

CSA, CSB

10, 11

8, 9

Chip Select (Active-LOW). These pins enable data transfers between the

user CPU and the SC16C752B for the channel(s) addressed. Individual

UART sections (A, B) are addressed by providing a logic LOW on the

respective CSA and CSB pins.

CTSA,

CTSB

38, 23

25, 16

Clear to Send (Active-LOW). These inputs are associated with individual

UART channels A and B. A logic 0 (LOW) on the CTS pins indicates the

modem or data set is ready to accept transmit data from the SC16C752B.

Status can be tested by reading MSR[4]. These pins only affect the transmit

and receive operations when Auto-CTS function is enabled via the Enhanced

Feature Register EFR[7] for hardware ﬂow control operation.

D0-D4,

D5-D7

44-48,

1-3

27-31, 32,

1-2

I/O

Data bus (bi-directional). These pins are the 8-bit, 3-state data bus for

transferring information to or from the controlling CPU. D0 is the least

signiﬁcant bit and the ﬁrst data bit in a transmit or receive serial data stream.

DSRA,

DSRB

39, 20

Data Set Ready (Active-LOW). These inputs are associated with individual

UART channels A and B. A logic 0 (LOW) on these pins indicates the modem

or data set is powered-on and is ready for data exchange with the UART. The

state of these inputs is reﬂected in the modem status register (MSR).

DTRA,

DTRB

34, 35

Data Terminal Ready (Active-LOW). These outputs are associated with

individual UART channels A and B. A logic 0 (LOW) on these pins indicates

that the SC16C752B is powered-on and ready. These pins can be controlled

via the modem control register. Writing a logic 1 to MCR[0] will set the DTR

output to logic 0 (LOW), enabling the modem. The output of these pins will

be a logic 1 after writing a logic 0 to MCR[0], or after a reset.

GND

Signal and power ground.

INTA, INTB

30, 29

21, 20

Interrupt A and B (Active-HIGH). These pins provide individual channel

interrupts INTA and INTB. INTA and INTB are enabled when MCR[3] is set to

a logic 1, interrupt sources are enabled in the interrupt enable register (IER).

Interrupt conditions include: receiver errors, available receiver buffer data,

available transmit buffer space, or when a modem status ﬂag is detected.

INTA, INTB are in the high-impedance state after reset.

IOR

Input/Output Read strobe (Active-LOW). A HIGH-to-LOW transition on

IOR will load the contents of an internal register deﬁned by address bits

A0-A2 onto the SC16C752B data bus (D0-D7) for access by external CPU.

IOW15

Input/Output Write strobe (Active-LOW). A LOW-to-HIGH transition on

IOW will transfer the contents of the data bus (D0-D7) from the external CPU

to an internal register that is deﬁned by address bits A0-A2 and CSA and

CSB.

n.c.

12, 24,

25, 37

Not connected.

SC16C752B 数据表(PDF) 5 Page - NXP Semiconductors

SC16C752B 数据表(HTML) 5 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

数据表下载