SC16C752B datasheet(7/47 Pages) PHILIPS

7 / 47 page

Philips Semiconductors

SC16C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Product data

Rev. 03 — 14 December 2004

7 of 47

9397 750 14443

Functional description

The SC16C752B UART is pin-compatible with the SC16C2550 UART. It provides

more enhanced features. All additional features are provided through a special

enhanced feature register.

The UART will perform serial-to-parallel conversion on data characters received from

peripheral devices or modems, and parallel-to-parallel conversion on data characters

transmitted by the processor. The complete status of each channel of the

SC16C752B UART can be read at any time during functional operation by the

processor.

The SC16C752B can be placed in an alternate mode (FIFO mode) relieving the

processor of excessive software overhead by buffering received/transmitted

characters. Both the receiver and transmitter FIFOs can store up to 64 bytes

(including three additional bits of error status per byte for the receiver FIFO) and have

selectable or programmable trigger levels. Primary outputs RXRDY and TXRDY allow

signalling of DMA transfers.

The SC16C752B has selectable hardware ﬂow control and software ﬂow control.

Hardware ﬂow control signiﬁcantly reduces software overhead and increases system

efﬁciency by automatically controlling serial data ﬂow using the RTS output and CTS

input signals. Software ﬂow control automatically controls data ﬂow by using

programmable Xon/Xoff characters.

The UART includes a programmable baud rate generator that can divide the timing

reference clock input by a divisor between 1 and (216

− 1).

6.1 Trigger levels

The SC16C752B provides independent selectable and programmable trigger levels

for both receiver and transmitter DMA and interrupt generation. After reset, both

transmitter and receiver FIFOs are disabled and so, in effect, the trigger level is the

default value of one byte. The selectable trigger levels are available via the FCR. The

programmable trigger levels are available via the TLR.

6.2 Hardware ﬂow control

Hardware ﬂow control is comprised of Auto-CTS and Auto-RTS. Auto-CTS and

Auto-RTS can be enabled/disabled independently by programming EFR[7:6].

With Auto-CTS, CTS must be active before the UART can transmit data.

Auto-RTS only activates the RTS output when there is enough room in the FIFO to

receive data and de-activates the RTS output when the RX FIFO is sufﬁciently full.

The halt and resume trigger levels in the TCR determine the levels at which RTS is

activated/deactivated.

If both Auto-CTS and Auto-RTS are enabled, when RTS is connected to CTS, data

transmission does not occur unless the receiver FIFO has empty space. Thus,

overrun errors are eliminated during hardware ﬂow control. If not enabled, overrun

errors occur if the transmit data rate exceeds the receive FIFO servicing latency.

SC16C752B 数据表(PDF) 7 Page - NXP Semiconductors

SC16C752B 数据表(HTML) 7 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

数据表下载