Philips Semiconductors

SC16C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Product data

Rev. 03 — 14 December 2004

8 of 47

9397 750 14443

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

6.2.1

Auto-RTS

Auto-RTS data flow control originates in the receiver block (see Figure 1 “Block

diagram.” on page 3). Figure 5 shows RTS functional timing. The receiver FIFO

trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO

level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger

level is reached, RTS is deasserted. The sending device (e.g., another UART) may

send an additional byte after the trigger level is reached (assuming the sending UART

has another byte to send) because it may not recognize the deassertion of RTS until

it has begun sending the additional byte. RTS is automatically reasserted once the

receiver FIFO reaches the resume trigger level programmed via TCR[7:4]. This

reassertion allows the sending device to resume transmission.

Fig 4.

Autoflow control (Auto-RTS and Auto-CTS) example.

RX

FIFO

FLOW

CONTROL

TX

FIFO

PARALLEL

TO SERIAL

TX

FIFO

RX

FIFO

UART 1

UART 2

D7 to D0

RX

TX

RTS

CTS

TX

RX

CTS

RTS

D7 to D0

002aaa228

SERIAL TO

PARALLEL

SERIAL TO

PARALLEL

FLOW

CONTROL

FLOW

CONTROL

FLOW

CONTROL

PARALLEL

TO SERIAL

(1) N = receiver FIFO trigger level.

(2) The two blocks in dashed lines cover the case where an additional byte is sent, as described in Section 6.2.1.

Fig 5.

RTS functional timing.

Start

byte N

Start

byte N

+ 1

Start

Stop

Stop

RX

RTS

IOR

N

N+1

12

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