SC16C752B datasheet(10/47 Pages) PHILIPS

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Philips Semiconductors

SC16C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Product data

Rev. 03 — 14 December 2004

10 of 47

9397 750 14443

There are two other enhanced features relating to software ﬂow control:

• Xon Any function (MCR[5]): Operation will resume after receiving any character

after recognizing the Xoff character. It is possible that an Xon1 character is

recognized as an Xon Any character, which could cause an Xon2 character to be

written to the RX FIFO.

• Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the

special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The

Xoff interrupt is cleared by a read of the IIR. The special character is transferred to

the RX FIFO.

6.3.1

When software ﬂow control operation is enabled, the SC16C752B will compare

incoming data with Xoff1,2 programmed characters (in certain cases, Xoff1 and Xoff2

must be received sequentially). When the correct Xoff character are received,

transmission is halted after completing transmission of the current character. Xoff

detection also sets IIR[4] (if enabled via IER[5]) and causes INT to go HIGH.

To resume transmission, an Xon1,2 character must be received (in certain cases

Xon1 and Xon2 must be received sequentially). When the correct Xon characters are

received, IIR[4] is cleared, and the Xoff interrupt disappears.

6.3.2

Xoff1/2 character is transmitted when the RX FIFO has passed the HALT trigger level

programmed in TCR[3:0].

Xon1/2 character is transmitted when the RX FIFO reaches the RESUME trigger

level programmed in TCR[7:4].

The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of

an ordinary byte from the FIFO. This means that even if the word length is set to be 5,

6, or 7 characters, then the 5, 6, or 7 least signiﬁcant bits of Xoff1,2/Xon1,2 will be

transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom

done, but this functionality is included to maintain compatibility with earlier designs.)

It is assumed that software ﬂow control and hardware ﬂow control will never be

enabled simultaneously. Figure 7 shows an example of software ﬂow control.

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