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PC97338VLJ 数据表(PDF) 41 Page - National Semiconductor (TI) |
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PC97338VLJ 数据表(HTML) 41 Page - National Semiconductor (TI) |
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41 / 221 page ![]() 41 www.national.com 2.3.1 Configuration Register Bitmaps 7 6 5 432 10 Register (FER) Reset Required Function Enable Index 00h 0 0 0 0 0 0 x x Parallel Port Enable SCC1 Enable SCC2 Enable FDC Enable FDC Four-Drive Encoding Select FDC Secondary Address Reserved Reserved 7 6 5 432 10 Register (FAR) Reset Required Function Address Index 01h 0 x 0 0 0 x 0 0 Parallel Port Address SCC1 Address SCC2 Address Select COM3 or COM4 7 6 5 432 10 Register (PTR) Reset Required Power and Test Index 02h 0 0 0 0 1 0 0 0 Power Down Reserved Reserved Select IRQ5 or IRQ7 SCC1 Test Mode Reserved Lock Configuration Select Extended or Compatible Parallel Port 7 6 5 432 10 Register (FCR) Reset Required Function Control Index 03h 1 0 0 0 0 0 0 0 0 0 TDR Mode Select Select ZWS or CS1 Parallel Port Float Control Clock Multiplier Test Bit Zero Wait State Enable Reserved Select MSEN0 or DRATE0 Reserved EPP Enable EPP Version Select ECP Enable ECP Clock Freeze Reserved Parallel Port Open-Drain Control Parallel Port Interrupt I/O Control 7 654 32 10 Register (PCR) Reset Required Parallel Port Control Index 04h 0 0 0 0 0 0 0 0 0 Reserved 7 654 32 10 (PMC) Reset Required Power Management Index 06h 0 0 0 0 0 0 0 0 7 654 32 10 (TUP) Reset Required Tape, SCCs and Parallel Port Index 07h 0 0 0 0 0 0 7 654 32 10 Register (SID) Reset Required Index 08h x x x 0 1 1 0 1 x x x 0 1 1 0 1 Control Register Reserved FDC TRI-STATE Control SCC1 TRI-STATE Control Reserved PD and IDLE or IRSL2/ID2 Enable Selective Lock PPM TRI-STATE Enable Reserved Configuration Register Reserved FDC 2 Mbps Enable EPP Time-Out Interrupt Enable Reserved(PC97338) / MIDI(PC87338) Reserved IDLE Status PD Status IDLE Pin Mask D0 D1 D2 D3 D4 D5 D6 D7 SuperI/O Chip Identification |
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