PC97338VLJ datasheet(13/221 Pages) NSC

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FIGURE 50 DSR Register Bitmap ................................................................................................................... 82

FIGURE 51 FDC Data Register Bitmap ........................................................................................................... 83

FIGURE 52 DIR Register Bitmap .................................................................................................................... 84

FIGURE 53 CCR Register Bitmap ................................................................................................................... 84

FIGURE 54 ST0 Result Phase Register Bitmap .............................................................................................. 88

FIGURE 55 ST1 Result Phase Register Bitmap .............................................................................................. 89

FIGURE 56 ST2 Result Phase Register Bitmap .............................................................................................. 90

FIGURE 57 ST3 Result Phase Register .......................................................................................................... 91

FIGURE 58 IBM, Perpendicular, and ISO Formats Supported by FORMAT TRACK Command .................... 99

FIGURE 59 PC87338/PC97338 Four Floppy Disk Drive Circuit ................................................................... 122

FIGURE 60 DTR Register Bitmap (SPP Mode) ............................................................................................. 125

FIGURE 61 STR Register Bitmap (SPP Mode) ............................................................................................. 125

FIGURE 62 CTR Register Bitmap (SPP Mode) in PC87338 ......................................................................... 126

FIGURE 63 CTR Register Bitmap (SPP Mode) in PC97338 ......................................................................... 126

FIGURE 64 DTR Register Bitmap (EPP Mode) ............................................................................................. 129

FIGURE 65 STR Register Bitmap (EPP Mode) ............................................................................................. 129

FIGURE 66 CTR Register Bitmap (EPP Mode) ............................................................................................. 130

FIGURE 67 DTR Register Bitmap (EPP Mode) ............................................................................................. 130

FIGURE 68 DTR Register Bitmap (EPP Mode) ............................................................................................. 130

FIGURE 69 DTR Register Bitmap (EPP Mode) ............................................................................................. 130

FIGURE 70 EPP Data Port 2 Bitmap ............................................................................................................. 130

FIGURE 71 EPP Data Port 3 Bitmap ............................................................................................................. 131

FIGURE 72 EPP 1.7 Address Write .............................................................................................................. 131

FIGURE 73 EPP 1.7 Address Read .............................................................................................................. 132

FIGURE 74 EPP Write with Zero Wait States ............................................................................................... 132

FIGURE 75 EPP 1.9 Address Write .............................................................................................................. 133

FIGURE 76 EPP 1.9 Address Read .............................................................................................................. 133

FIGURE 77 DATAR Register Bitmap ............................................................................................................ 136

FIGURE 78 AFIFO Register Bitmap .............................................................................................................. 137

FIGURE 79 ECP DSR Register Bitmap ......................................................................................................... 137

FIGURE 80 DCR Register Bitmap ................................................................................................................. 137

FIGURE 81 CFIFO Register Bitmap .............................................................................................................. 138

FIGURE 82 DFIFO Register Bitmap .............................................................................................................. 139

FIGURE 83 TFIFO Register Bitmap .............................................................................................................. 139

FIGURE 84 CNFGA Register Bitmap ............................................................................................................ 139

FIGURE 85 CNFGB Register Bitmap ............................................................................................................ 140

FIGURE 86 ECR Register Bitmap ................................................................................................................. 140

FIGURE 87 ECP Forward Write Cycle .......................................................................................................... 142

FIGURE 88 ECP (Reverse) Read Cycle ....................................................................................................... 143

FIGURE 88 Composite Serial Data ............................................................................................................... 146

FIGURE 88 Register Bank Architecture ........................................................................................................ 153

FIGURE 88 Interrupt Enable Register ........................................................................................................... 154

FIGURE 88 Event Identification Register, Non-Extended Mode ................................................................... 155

FIGURE 88 Event Identification Register, Extended Mode ........................................................................... 156

FIGURE 88 FIFO Control Register ................................................................................................................ 157

FIGURE 88 Link Control Register .................................................................................................................. 158

FIGURE 88 Modem Control Register, Non-Extended Mode ......................................................................... 159

FIGURE 88 Modem Control Register, Extended Modes ............................................................................... 159

FIGURE 88 Link Status Register ................................................................................................................... 160

FIGURE 88 Modem Status Register .............................................................................................................. 162

FIGURE 88 Auxillary Status and Control Register ....................................................................................... 162

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