PC97338VLJ datasheet(49/221 Pages) NSC

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Bit 1 - Select MSEN0 or DRATE0

This bit is initialized to 0 during reset, thus select-

ing MSEN0.

0 - MSEN0 is selected on the pin. (Default)

1 - DRATE0 is selected on the pin.

Bit 2 - Reserved

This bit is reserved.

Bit 3 - Parallel Port Multiplexor (PPM) Float

Control

When this bit is zero, the PPM pins are driven.

Otherwise, they are in TRI-STATE. Bit 3 is also

functional when the PPM is not configured. (The

PPM is configured when bits 7,6 of SIRQ3 are 10,

and bit 1 of SCF3 is 0.)

When this bit is set the PPM output signals are in

TRI-STATE and the input signals are blocked to re-

duce their leakage current. The values of the

blocked

input

signals

are:

BUSY=1,

PE=0,

SLCT=0, ACK=1 and ERR=1.

To avoid undefined FDC input signals, the PPM

can be disabled before this bit is set.

0 - The PPM pins are driven.

1 - The PPM pins are in TRI-STATE and the pul-

lup resistors are disconnected.

Bit 4 - Reserved

This bit is reserved and is always 0.

Bit 5 - Zero Wait State Enable

0 - No ZWS enabled.

1 - If pin 3 is configured as ZWS (see bit 6), ZWS

is driven low when the Enhanced Parallel Port

(EPP) or the ECP can accept a short host

read/write-cycle; otherwise the ZWS open

drain output signal is not driven. EPP ZWS

operation should be configured when the sys-

tem’s device is fast enough to support it.

Bit 6 - Select ZWS or CS1 on pin 3

0 - ZWS function is selected on pin 3.

1 - CS1 function is selected on pin 3

Bit 7 - Reserved

Reserved bit. Write 0.

2.3.6

Printer Control Register (PCR),

Index 04h

This register enables the EPP, ECP, version modes,

and interrupt options. See Table 15.

TABLE 15. Parallel Port Mode

On reset all the bits of PCR are cleared to 0.

FIGURE 7. PCR Register Bitmap

Bit 0 - EPP Enable

0 - The EPP is disabled, and the EPP registers

are not accessible (access ignored).

1 - If bit 2 of PCR is 0, the EPP is enabled. The

EPP should not be configured with base ad-

dress 3BCh.

Bit 1 - EPP Version Select

0 - Version 1.7 is supported.

1 - Version 1.9 is supported (IEEE 1284).

Bit 2 - ECP Enable

Enables or disables ECP mode. In Plug and Play

mode, IRQ7-3, IRQ12-9 or IRQ15 are selected via

the PNP0 register.

0 - The ECP is disabled and in power-down

mode. The ECP registers are not accessible

(access ignored), the ECP interrupt is inactive

and DMA request pin is in TRI-STATE. The

IRQ5,7 input signals are blocked to reduce

their leakage currents.

1 - The ECP is enabled. The software should

change this bit to 1 only when bits 2-0 of the

existing CTR are 100.

Operation

Mode

Bit 0 of

FER

Bit 7 of

PTR

Bit 0 of

PCR

Bit 2 of

PCR

None

Compatible

Extended

EPP

ECP

EPP Enable

EPP Version Select

ECP Enable

ECP Clock Freeze Control

Reserved

Parallel Port Open-Drain Control

Parallel Port Interrupt I/O Control

543

Reset

Required

Parallel Port Control

Index 04h

Reserved

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