PC97338VLJ datasheet(65/221 Pages) NSC

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TABLE 29. SIRQI2 Plug and Play Interrupt Map-

ping

Bit 4 - Invert SIRQI2

In the following, x may equal 3, 4, 5, 6, 7, 9, 10, 11,

12 or 15, according to bits 3-0 of this register.

0 - SIRQI2 is not inverted. IRQx = SIRQI2.

1 - SIRQI2 is inverted. IRQx = inverted SIRQI2.

Bit 5 - SIRQI2 Status

This bit is read-only. It holds the value of SIRQI2,

when SIRQI2 controls its pin.

Bits 7,6 - Select MSEN1, DRATE1, CS0 or SIRQI2

These bits are ignored when bit 0 of the SCF3 reg-

ister is 1. Setting bit 0 of the SCF3 register to 1

gives DACK3 control of the pin it shares with

MSEN1, DRATE1, CS0 and SIRQI2.

Table 30 shows how the values of these bits con-

trol which signal uses the pin they share.

TABLE 30. Selecting MSEN1, DRATE1, CS0 or

SIRQI2

2.3.35 System IRQ Input 3 Configuration

This register allows configuration of the SIRQI3 sig-

nal. See Table 32.

SIRQ3 is initialized to 00x00000 during reset.

FIGURE 37. SIRQ3 Register Bitmap

Bits 3-0 - SIRQI3 Mapping

When SIRQI3 controls its pin, it can be routed onto

one of the following ISA interrupts: IRQ3-IRQ7,

IRQ9-IRQ12 and IRQ15. See Table 31.

Unpredictable results when invalid values are writ-

ten. IRQ5, IRQ12 and IRQ15 can not always be

configured. For more details, refer to Section 6.

It is the software‘s responsibility to route all inter-

rupt sources onto the ISA interrupts correctly.

Bit 3

Bit 2

Bit 1

Bit 0

Interrupt

Disable

Invalid

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

Invalid

IRQ9

IRQ10

IRQ11

IRQ12

Invalid

IRQ15

Bit 0 of

SCF3

Bit 7 of

SIRQ2

Bit 6 of

SIRQ2

Signal that

Uses the Pin

MSEN1

DRATE1

CS0

SIRQI2

DACK3

Select DRV2, DR23, PNF or SIRQI3

543

Reset

Required

(SIRQ3)

System IRQ Input 3

Index 4Eh

Configuration Register

Invert SIRQI3

SIRQI3 Status

SIRQI3 Mapping

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