PC97338VLJ datasheet(85/221 Pages) NSC

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3.4

THE PHASES OF FDC COMMANDS

FDC commands may be in the command phase, the

execution phase or the result phase. The active

phase determines how data is transferred between

the Floppy Disk Controller (FDC) and the host micro-

processor. When no command is in progress, the

FDC may be either idle or polling a drive.

3.4.1

Command Phase

During the command phase, the microprocessor

writes a series of bytes to the Data Register (FIFO).

The first command byte contains the opcode for the

command, which the controller can interpret to deter-

mine how many more command bytes to expect. The

remaining command bytes contain the parameters re-

quired for the command.

The number of command bytes varies for each com-

mand. All command bytes must be written in the order

specified in the Command Description Table in Sec-

tion 3.6 on page 91. The execution phase starts im-

mediately after the last byte in the command phase is

written. Prior to performing the command phase, the

Digital Output Register (DOR) should be set and the

data rate should be set with the Data rate Select Reg-

ister (DSR) or the Configuration Control Register

(CCR).

The Main Status Register (MSR) controls the flow of

command bytes, and must be polled by the software

before writing each command phase byte to the Data

7 of MSR (RQM, Request for Master) must be set and

bit 6 of MSR (DIO, Data I/O direction) must be

cleared.

After the first command byte is written to the Data

mand in Progress) is also set and remains set until the

last result phase byte is read. If there is no result

phase, the CMD PROG bit is cleared after the last

command byte is written.

A new command may be initiated after reading all the

result bytes from the previous command. If the next

command requires selection of a different drive or a

change in the data rate, the DOR and DSR or CCR

should be updated, accordingly. If the command is the

last command, the software should deselect the drive.

Normally, command processing by the controller core

and updating of the DOR, DSR, and CCR registers by

the microprocessor are operations that can occur in-

dependently of one another. Software must ensure

that the these registers are not updated while the con-

troller is processing a command.

3.4.2

Execution Phase

During the execution phase, the Floppy Disk Control-

ler (FDC) performs the desired command.

Commands that involve data transfers (e.g., read,

write and format operations) require the microproces-

sor to write or read data to or from the Data Register

(FIFO) at this time. Some commands, such as SEEK

or RECALIBRATE, control the read/write head move-

ment on the disk drive during the execution phase via

the disk interface signals. Execution of other com-

mands does not involve any action by the micropro-

cessor or disk drive, and consists of an internal

operation by the controller.

Data can be transferred between the microprocessor

and the controller during execution in DMA mode, in-

terrupt transfer mode or software polling mode. The

last two modes are non-DMA modes. All data transfer

modes work with the FIFO enabled or disabled.

DMA mode is used if the system has a DMA control-

ler. This allows the microprocessor to do other tasks

while data transfer takes place during the execution

phase.

If a non-DMA mode is used, an interrupt is issued for

each byte transferred during the execution phase. Al-

so, instead of using the interrupt during a non-DMA

mode transfer, the Main Status Register (MSR) can

be polled by software to indicate when a byte transfer

is required.

DMA Mode - FIFO Disabled

DMA mode is selected by writing a 0 to the DMA bit in

the SPECIFY command and by setting bit 3 of the

DOR (DMA enabled) to 1.

In the execution phase when the FIFO is disabled,

each time a byte is ready to be transferred, a DMA re-

quest (DRQ) is generated in the execution phase. The

DMA controller should respond to the DRQ with a

DMA acknowledge (DACK) and a read or write pulse.

The DRQ is cleared by the leading edge of the active

low DACK input signal. After the last byte is trans-

ferred, an interrupt is generated, indicating the begin-

ning of the result phase.

During DMA operations, FDC address signals are ig-

nored since AEN input signal is 1. The DACK signal

acts as the chip select signal for the FIFO, in this

case, and the state of the address lines A2-0 is ig-

nored. The Terminal Count (TC) signal can be assert-

ed by the DMA controller to terminate the data

transfer at any time. Due to internal gating, TC is only

recognized when DACK is low.

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