STNRGPF01 datasheet(13/40 Pages) STMICROELECTRONICS

13 / 40 page

DocID030377 Rev 2

13/40

STNRGPF01

STNRGPF01 block diagram

The output level of COMP3 and COMP2 are used to generate the master PWM[0]. The

SYNCR[1] and SYNCR[2] inputs are triggered respectively on the rising and falling edge of

the PWM[0]. These trigger signals are sent to interleaving blocks which generate the phase

shifted (120º/180º and 240º) ON/OFF signals for the other channels.

The SET[1], SET[2], RESET[1] and RESET[2] (pins: 4, 5, 8, 16) signals must be connected

to external devices (for example two flip-flops) in order to obtain the driving signals PWM1

and PWM2.

The ENABLE input (pin 18) performs a protection function. The connection to the CLOCK

signal (pin 2 at switching frequency) prevents undesired commutation of the PWM[0] and

consequently on the other channels.

3.5

Programming section

Device programming is done by using a PC with dedicated loader software (STNRG

LOADER), an FTDI cable and an adapter board (see Figure 8).

Figure 8. Programming section

STNRGPF01 数据表(PDF) 13 Page - STMicroelectronics