STNRGPF01 datasheet(19/40 Pages) STMICROELECTRONICS

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STNRGPF01

Pinout and pin description

4.2

Pin description

Table 2. Pin description

No. Type(1)

Name

Pin description

PWM[0]

This pin generates the PWM[0] for the master channel CH0.

CLOCK

This pin generates a PWM signal at selected working frequency with a duty cycle of

50%. This signal is used to generate triangular waveforms at switching frequency by

means of an external op-amp. The CLOCK signal is also used to implement

protection against undesired commutations.

SYNCR[1]

This pin receives the PWM[0] signal in order to synchronize the other channels. The

rising edge of the PWM[0] signal is used to trigger ON the slave channels CH1 and

CH2.

SET[1]

This pin generates a pulse in order to set to ON the CH1 channel with the right out-

of-phase. This out-of-phase will be 120° electrical degrees when three channels are

activated and 180° when only two channels work. This pin is connected to a SET pin

of an external flip-flop in order to start the conduction of the CH1.

RESET[1]

This pin generates a pulse in order to set OFF the CH1 channel with the right out-of-

phase. This out-of-phase will be 120° electrical degrees when three channels are

activated and 180° when only two channels work. This pin is connected to a RESET

pin of an external flip-flop in order to stop the conduction of the CH1.

SYNCR[2]

This pin receives the PWM[0] signal in order to synchronize the other channels. The

falling edge of the PWM[0] signal is used to trigger OFF the slave channels CH1 and

CH2.

NC[1]

Reserved

RESET[2]

This pin generates a pulse in order to set OFF the CH2 channel with out-of-phase of

240°. This pin is connected to a RESET pin of an external flip-flop in order to stop the

conduction of the CH2.

NC[2]

Reserved

I/O

NRST

Reset

VDD

Supply voltage

VSS

Ground

VCOUT

Supply voltage of the digital section. An external capacitor must be connected to the

VCOUT pin.

PFC_FAULT During normal operation this pin is high. If a fault condition occurs it is forced low.

PFC_OK

When the PFC has completed the start-up procedure, this pin is forced low. During

the start-up phase or when in fault condition, this pin is high.

SET[2]

This pin generates a pulse in order to set ON the CH2 channel with out-of-phase of

240°. This pin is connected to a SET pin of an external flip-flop in order to start the

conduction of the CH2.

ZVD

This pin receives a square wave signal synchronized with input AC voltage. The

rising edge of the square wave signal is used by the STNRGPF01 to detect the ZVD

instant.

ENABLE

This pin receives the CLOCK signal in order to avoid undesired commutation.

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