SRC0 datasheet(12/48 Pages) STMICROELECTRONICS

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Operation

SRC0

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DocID026008 Rev 2

Operation

The SRC0 simplified smart push-button on/off controller with Smart Reset and power-on

lockout enables and disables power for the application depending on push-button states,

signals from the processor, and battery voltage.

Power-on

Because most of the processors have outputs in high-Z state before initialization, an internal

pull-down resistor is connected to PSHOLD input during startup (see Figure 7, 8, 9, 10, 11,

12, 13, and 18).

To power up the device the push-button PB has to be pressed for at least tDEBOUNCE and

VCC has to be above VTH+ for the whole tDEBOUNCE period. If the battery voltage drops

below VTH+ during the tDEBOUNCE, the counter is reset and starts to count again when VCC >

VTH+ (see Figure 13). After tDEBOUNCE the enable signal is asserted (EN goes high, EN

goes low), reset output RST is asserted for tREC and then the startup routine is performed by

the processor. During initialization, the processor sets the PSHOLD signal high.

On the SRC0 the PSHOLD signal has to be set high prior to push-button release and

tON_BLANK expiration, otherwise the enable signal is deasserted (EN goes low, EN goes

high) - see Figure 7, 8, 9, and 10. The time up to push-button release represents the

maximum time allowed for the system to power up and initialize the circuits driving the

PSHOLD input. If the PSHOLD signal is low at push-button release, the enable output is

deasserted immediately, thus turning off the system power. If tON_BLANK expires prior to

push-button release, the PSHOLD state is checked at its expiration. This safety feature

disables the power and prevents discharging the battery if the push-button is stuck or it is

held for an unreasonable period of time and the application is not responding (see Figure 8

and 10). PB status, INT status and VCC undervoltage detection are not monitored until

power-up is completed.

Push-button interrupt

If the device works under normal operation (i.e. PSHOLD is high) and the push-button PB is

pressed for more than tDEBOUNCE, a negative pulse with minimum tINT_Min width is

generated on the INT output. By connecting INT to the processor interrupt input (INT or

NMI) a safeguard routine can be performed and the power can be shut down by setting

PSHOLD low - see Figure 14.

Forced power-down mode

The PSHOLD output can be forced low anytime during normal operation by the processor

and can deassert the enable signal - see Figure 14.

Undervoltage detection

If VCC voltage drops below VTH- voltage threshold during normal operation, the INT output is

driven low (see Figure 20 and Figure 21).

If an undervoltage condition is detected for tDEBOUNCE + tINT_Min + tSRD, the enable output is

deasserted (see Figure 21).

Hardware reset or power-down while system not responding

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