SRC0 datasheet(24/48 Pages) STMICROELECTRONICS

24 / 48 page

Waveforms

SRC0

24/48

DocID026008 Rev 2

Figure 18. Long push (option with RST assertion)

tSRD period is set by external capacitor CSRD.

PB ignored during tINT_Min.

PSHOLD signal is ignored during tON_BLANK. Its level is checked after tON_BLANK expires and if it is high the

EN signal remains asserted, otherwise EN goes low.

Internal pull-down resistor 300 k

 is connected to PS

HOLD input during startup when device is reset.

internal pull-down resistor

connected to PS

HOLD

input

HOLD

ignored

PB status

ignored

tON _BLANK

tSR D

(1)

set by C SR D

V CC undervoltage detection status ignored

HOLD

(3, 4)

INT

(2)

RST

Push-button pressed

and PB connected to

GND

tDEBOUNCE

tREC

Push-button held even

after tSRD expires

therefore RST is asserted

INT can go high , if PB goes high,

but system freezes and processor

won’t respond

if system freezes, processor won’t

respond to any INT status change

tINT _Min

tDEBOUNCE

After tON _BLANK

PB is monitored

for falling edge

ON _BLANK expires

HOLD

state detected as high

therefore EN remains high

AM00252v3

Note: EN is high.

SRC0 数据表(PDF) 24 Page - STMicroelectronics

SRC0 数据表(HTML) 24 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

数据表下载

链接网址

SRC0 数据表(PDF) 24 Page - STMicroelectronics

SRC0 数据表(HTML) 24 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

数据表 下载

链接网址

数据表下载