DocID026008 Rev 2

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SRC0

DC and AC characteristics

48

(5)

Output high voltage

enable asserted

0.3

V

(6)

enable off to enable on

64

88

ms

EN, EN leakage current

–0.1

+0.1

µA

RST

Output low voltage

RST asserted

0.3

V

RST pulse width

240

360

480

ms

RST leakage current

–0.1

+0.1

µA

INT

Output low voltage

INT asserted

0.3

V

Minimum INT pulse width

32

44

ms

INT leakage current

–0.1

+0.1

µA

1.5 V voltage reference

100 k

 and mandatory 1 µF

1.485

–1%

1.5

1.515

+1%

V

1.

2.

3.

This blanking time allows the processor to start up correctly (see Figure 7, 8, 9, 10, 11, 12).

4.

The internal pull-up resistor connected to the SR input is optional.

5.

Valid for push-pull only.

6.

Minimum delay time between enable deassertion and enable reassertion, allowing the application to complete the power-

down properly. PB is ignored during this period.

Table 5. DC and AC characteristics (continued)

Symbol

Parameter

Min.

Max.

Unit