ST7MC1K2 datasheet(168/371 Pages) STMICROELECTRONICS

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Clock deviation causes

The causes which contribute to the total deviation are:

●

DTRA: deviation due to transmitter error.

Note:

The transmitter can be either a master or a slave (in case of a slave listening to the

response of another slave).

●

DMEAS: error due to the LIN synch measurement performed by the receiver.

●

DQUANT: error due to the baud rate quantization of the receiver.

●

DREC: deviation of the local oscillator of the receiver: This deviation can occur during

the reception of one complete LIN message assuming that the deviation has been

compensated at the beginning of the message.

●

DTCL: deviation due to the transmission line (generally due to the transceivers)

All the deviations of the system should be added and compared to the LINSCI clock

tolerance:

DTRA + DMEAS +DQUANT + DREC + DTCL < 3.75%

Figure 72.

Bit sampling in reception mode

Error due to LIN synch measurement

The LIN synch field is measured over eight bit times.

This measurement is performed using a counter clocked by the CPU clock. The edge

detections are performed using the CPU clock cycle.

This leads to a precision of 2 CPU clock cycles for the measurement which lasts 16*8*LDIV

clock cycles.

Consequently, this error (DMEAS) is:

2/(128*LDIVMIN).

LDIVMIN corresponds to the minimum LIN prescaler content, leading to the maximum baud

rate, taking into account the maximum deviation of

±15%.

RDI line

Sample

Sampled values

One bit time

6/16

7/16

clock

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