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ST7MC1K2 数据表(PDF) 177 Page - STMicroelectronics

部件名 ST7MC1K2
功能描述  Clock, reset and supply management
PDF  371 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7MC1K2 数据表(HTML) 177 Page - STMicroelectronics

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Obsolete
Product(s)
- Obsolete
Product(s)
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
On-chip peripherals
177/371
Note:
1
When initializing LDIV, the LPFR register must be written first. Then, the write to the LPR
register effectively updates LDIV and so the clock generation.
2
In LIN Slave mode, if the LPR[7:0] register is equal to 00h, the transceiver and receiver input
clocks are switched off.
Examples of LDIV coding
Example 1: LPR = 27d and LPFR = 12d
This leads to:
Mantissa (LDIV) = 27d
Fraction (LDIV) = 12/16 = 0.75d
Therefore LDIV = 27.75d
Example 2: LDIV = 25.62d
This leads to:
LPFR = rounded(16*0.62d) = rounded(9.92d) = 10d = Ah
LPR = mantissa (25.620d) = 25d = 1Bh
Example 3: LDIV = 25.99d
This leads to:
LPFR = rounded(16*0.99d) = rounded(15.84d) = 16d
The carry must be propagated to the mantissa: LPR = mantissa (25.99) +
1 = 26d = 1Ch.
LIN header length register (LHLR)
Note:
In LIN slave mode when LASE = 1 or LHDM = 1, the LHLR register is accessible at the
address of the SCIERPR register.
Otherwise this register is always read as 00h.
Table 75.
LDIV fractions
LPFR[3:0]
Fraction (LDIV)
0h
0
1h
1/16
...
...
Eh
14/16
Fh
15/16
LHLR
Reset value: 0000 0000 (00h)
7
654
32
10
LHLR[7:0]
RO
Obsolete
Product(s)
- Obsolete
Product(s)



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