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ST7MC1K2 数据表(PDF) 191 Page - STMicroelectronics |
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ST7MC1K2 数据表(HTML) 191 Page - STMicroelectronics |
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191 / 371 page  Obsolete Product(s) - Obsolete Product(s) ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto On-chip peripherals 191/371 Figure 79. Input stage in sensorless or sensor mode (bits TES[1:0] = 00) 1. Preload register; changes taken into account at next C event VREF Inputn sel reg VR[2:0] MCIC MCIA MCIB A B C IS[1:0] CS,H 00 01 10 + - Input block Input comparator block Event detection D Q CP ZVD bit HDMn bit (1) to ZH generation or or or or 1 2 CPBn bit (1) REO bit CS,H DS,H CPBn bit (1) V I 12-bit PWM generator signal U Sampling frequency Sample CS,H DS,H MPHST register MPOL register MCRA register MCRB register MPOL register MCRB register Reg C DS,H Z Events Commutation BEMF zero-crossing End of demagnetization E Emergency stop Notes Updated/shifted on R Ratio updated (+1 or -1) Multiplier overflow R+/- O Current mode Voltage mode I V Regn Updated with regn+1 1 2 Branch taken after C MCRC register MCVREF PZ bit MCRA register 111 Sample SPLG bit MCRC register SR bit MCONF register DS[3:0] bits 2 1 DWF[3:0] MDFR register ZWF[3:0] MZFR register SR bit MCRA register to DH generation Z event generation D event generation fSCF V0C1 bit MCRA register on C event Branch taken after D event Obsolete Product(s) - Obsolete Product(s) |
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