ST7MC1K2 datasheet(193/371 Pages) STMICROELECTRONICS

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On-chip peripherals

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The comparator output is processed by a detector that automatically recognizes the D or Z

event, depending on the CPB or ZVD edge and level configuration bits as described in

Table 88.

To avoid wrong detection of D and Z events, a blanking window filter is implemented for

spike filtering. In addition, by means of an event counter, software can filter several

consecutive events up to a programmed limit before generating the D or Z event internally.

This is shown in Figure 80 and Figure 81.

D event detection

In sensorless mode, the D window filter becomes active after each C event. It blanks out the

D event during the time window defined by the DWF[3:0] bits in the MDFR register (see

Table 84). The reset value is 200µs.

This window filter becomes active after both hardware and software C events.

The D event filter becomes active after the D window filter. It counts the number of

consecutive D events up to a limit defined by the DEF[3:0] bits in the MDFR register. The

reset value is 1. The D bit is set when the counter limit is reached.

Sampling is done at a selectable frequency (fSCF), see Table 166.

The D event filter is active only for a hardware D event (DH). For a simulated (DS) event, it is

forced to 1.

Figure 80.

D window and event filter flowchart

End of blanking

D event?

Sampling

Limit = 1?

Reset counter

Increment counter

Set the D bit

Counter = limit?

Yes

Window

filter

Event

filter

window?

Yes

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