ST7MC1K2 datasheet(285/371 Pages) STMICROELECTRONICS

285 / 371 page

Obsolete

Product(s)

- Obsolete

Product(s)

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto

On-chip peripherals

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Parity register (MPAR)

3SOI

Sampling out interrupt flag

This interrupt indicates that the sampling that should have been done during Ton

has occurred during the next Toff. In this case, the sample is discarded.

0: No sampling out interrupt pending

1: Sampling out interrupt pending

2SOM

Sampling out mask bit

This interrupt is available only for Z event sampling as D event sampling is always

done at fSCF high frequency.

0: Sampling out interrupt disabled

1: Sampling out interrupt enabled

This interrupt is available only when a delay has been set in the DS[3:0] bits in the

MCONF register.

Note: It is recommended to disable the sampling out interrupt when software Z

event is enabled (SZ bit in MCRC register is set) and if the value in the DS[3:0]

bits is modified to change the sampling method during the application.

1:0 XT16:XT8

BLDC drive motor control peripheral input frequency selection

00: fPERIPH (peripheral frequency) = fMTC

01: fPERIPH (peripheral frequency) = fMTC/2

10: fPERIPH (peripheral frequency) = fMTC/4

11: fPERIPH (peripheral frequency) = fMTC/4 (same as XT16 = 1, XT8 = 0)

Caution: It is recommended to set the peripheral frequency to 4 MHz. Setting

fPERIPH =fMTC is used mainly when fclk = 4 MHz (for low power consumption).

Times are indicated for 4 MHz fPERIPH.

MPAR

Reset value: 0000 0000 (00h)

654

TES[1:0]

OE[5:0](1)

Preload bits, new value taken into account at the next C event (in normal mode) or when a value is written

in the MPHST register when in direct access mode. For more details refer to the description of the DAC bit

in Control register A (MCRA) on page 265. The use of a preload register allows all the registers to be

updated at the same time.

R/W

Table 161.

MPAR register description

Bit

Name

Function

7:6

TES[1:0]

Tacho edge selection bits

The primary function of these bits is to select the edge sensitivity of the

tachogenerator capture logic; clearing both TES[1:0] bits specifies that the input

detection block does not operate in speed sensor mode but either in position

sensor or sensorless mode for a six-step motor drive). See Table 162.

5:0

OE[5:0]

Output parity mode

0: Output channel is High

1: Output channel Low

Note: These bits are not significant when PCN = 1 (configuration with three

independent phases).

Table 160.

MCONF register description (continued)

Bit

Name

Function

Obsolete

Product(s)

- Obsolete

Product(s)

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